On Tue, 23 Sep 2008, Sebastian Kuzminsky wrote:
> Date: Tue, 23 Sep 2008 20:24:42 -0600
> From: Sebastian Kuzminsky <[EMAIL PROTECTED]>
> Reply-To: "Enhanced Machine Controller (EMC)"
> <emc-users@lists.sourceforge.net>
> To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net>
> Subject: Re: [Emc-users] stepgen & pwmgen fixes
>
> Peter C. Wallace wrote:
>> On Tue, 23 Sep 2008, Eric H. Johnson wrote:
>>> Sebastian,
>>>
>>> Can you check to see that the pwmgen.enable is working properly. I was
>>> running samples all day (which looked great, btw, after resolving a very odd
>>> problem) so I did not have a chance to do much testing. I am now dropping
>>> the enable when the shutter closes, however the pwmgen.value is still
>>> getting values. The laser was still coming on even when the enable was low.
>>>
>>> I will try setting the frequency of the pwm from the latest update and
>>> hopefully test that tomorrow.
>>
>> Well I'm not Sebastian, but I know why you are seeing that behavior:
>>
>> The enable register was designed for our PWM and Analog output daughter cards
>> so it doesnt actually affect the PWM output, its just a group of (active low)
>> output bits used to enable the daughter card output channels. I can certainly
>> change this behavior so that the PWM output is forced low when a channel is
>> not enabled (cheap in terms of FPGA hardware). The active low enable output
>> is
>> used to guarantee that the motor drive outputs are off at power up (or
>> watchdog bite)
>>
>> I dont think there are any bad side effects of forcing the PWM output low if
>> disabled, but there are possible bad side effect of using a active high PWM
>> output without the enable (Laser is on high at power up unless you have some
>> other active low enable signal)
>
> The driver & firmware currently communicate the pwmgen.XX.enable pin to
> the /Enable IO pin on the IO connector (I just re-checked this).
> Peter's got a good argument for why the value of the PWM pin shouldnt
> matter to the downstream equipment if the /Enable IO pin is high.
>
> Eric, how are you handling the start-up condition (and potentially the
> watchdog condition) that Peter is describing?
>
> What would it mean to keep the PWM IO pin low if the .enable HAL pin is
> low? Should the FPGA *not* let the PWM pin go to high-impedance/pullup
> at bootup and at watchdog bite?
>
The PWM pin would only be forced low when the channel is disabled in the PWM
enable register. After Watchdog bite and at bootup, all I/Os would be in the
high state.
Still think best is to use the active low PWM enable output as separate
hardware enable, perhaps moved to one of the GPIO pins if a 7I37 is used to
enable the laser.
Peter Wallace
Mesa Electronics
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