Gene Heskett wrote: > Maybe I'm being cautious, but if I hooked my scope to the FET's gate, and saw > transition times noticeably slower than my 100mhz dual trace's own rise times > for it to make that about 20 volt swing, then I would be looking for ways to > speed up the driver. Even 30ns rise & fall times will be reflected in the > increased temps of the FET's as the current rises toward the max ratings. > > Well, generally, you can't go that fast in full-bridge switching applications. When feeding current to an inductive load, there is one side of the bridge sourcing current. When you switch that side to ground, the inductive effect draws current, and the common terminal between the high-side and low-side transistors tends to go below ground until the low-side transistor turns on completely. Most dual FET driver chips can only handle a limited amount of negative voltage there. As the Di/Dt rises, the voltages generated across even short, wide circuit traces becomes enormous, it is easy to see 20 V across a 2" trace. Circuit board layout only helps up to a point. When you reach the limit, slowing down the transistors is the last fix. With relatively slow PWM frequencies, a couple hundred ns rise and fall will not cause excessive losses. When you get to the 100 KHz and up range, then you have to work harder.
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