On Mon, 5 Apr 2010, Erik Christiansen wrote:

> Date: Mon, 5 Apr 2010 23:38:59 +1000
> From: Erik Christiansen <dva...@internode.on.net>
> Reply-To: emc-users@lists.sourceforge.net
> To: emc-users@lists.sourceforge.net
> Subject: [Emc-users] Estop strategy for Hostmot2 (7i40 x 2 + 7i37)
> 
> I'm about to wire in an NVR (No-Volt Release), i.e. a latching relay,
> set by a momentary pushbutton [1], but have a couple of questions:
>
> A) Is it safe to interrupt Motor Power to my 7i40s, with hairy great
>   inductive motors on their outputs? (OK, mostly resistive under load,
>   but then back EMF might also be deadly if V+ is open-circuited?)

Should be, the 7I40 has overvoltage protection, but this cannot be depended on 
for repeated faults (board thermal limit)

>
>   I can't use the 7i40's active low enable inputs, because they're in
>   the ribbon cable to the 5i20.
>
>   That means we have to go via the 7i37 inputs and the EMC2 software,
>   if we're to avoid potentially stressing the 7i40s.
>
>   Ah ... maybe interrupt Motor Power before the filter capacitors? That
>   leaves somewhere to dump back EMF, and should be gentler on the
>   H-bridges. (A bit rough on a relay though, with zero volts on the
>   capacitors at start-up. A fat MOSFET would handle it better.)

A good Estop system is to disconnect servo primary power and at the same time 
discharge the servo filter capacitors with a resistor for .5 - 1 second decay 
time. This will brake the motors so the voltage decay should not be too fast.

>
> B) What about a charge-pump? i.e. Estop if the controller goes down or
>   loses the plot. Or does the 5i20 do that in the FPGA?

There is a watchdog in the FPGA. It will reset all I/O to the power up state 
if not accessed at the preset interval. I would  not depend too much on this 
as a software/hardware failure of some kind might let the watchdog petting 
thread continue while the rest is going crazy.

>
>   I've read the "5i20 Anything I/O Manual", but the Hostmot2 section is
>   a bit thin. (Re the wiki, see below.)
>
>   But even if the 5i20 does disable the 4 H-bridges, that still leaves
>   the spindle whirring away. Does it tell EMC, so that I can
>   "net estop-out => some_7i30_output", to interrupt the Estop chain,
>   and cut spindle power as well?

Its watchdog will disable all I/O, (turn off all 7I37 outputs for example) so 
this will happen automatically on a watchdog bite but an output in series with 
the Estop chain is also good so EMC has an input to the chain for less severe
faults/user-input

>
> Finding only http://wiki.linuxcnc.org/cgi-bin/emcinfo.pl?EstopChain in
> the wiki, which just points to
> http://wiki.linuxcnc.org/cgi-bin/emcinfo.pl?MazakEstopChain , I wonder
> if:
>
> C) Is the HAL "estop latch" mentioned there just FYI? Point 26 raises
>   the issue of ESTOP_RESET, but point 27 says "ESTOP_RESET comes from
>   the core of EMC, and is asserted when the machine is taken out of
>   ESTOP (by hitting F1)."
>
>   So there appears to be no physical input needed for that. (But maybe
>   I should spraypaint F1 green.)
>
> D) Have I missed (in the wiki) a concise schematic showing a typical
>   Estop chain, useful relay contacts, and estop-in & estop-out wiring
>   and HAL config? Or is that a ToDo that I'm cheerfully walking into?
>   ;-)
>
> I hope that I'm expressing all that clearly, it's nearly midnight here.
>
> Erik
>
> [1] I'll try to use the existing Big Red Button on the mill, even if I
>    have to add a relay in the control box, to gain a free pair of
>    output contacts to go to the Estop chain.
>
> -- 
> You really HAVE to have a hardware E-stop!
>                                    - Jon Elson on emc-users, 14 Jun 2008.
>
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Peter Wallace
Mesa Electronics

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------------------------------------------------------------------------------
Download Intel&#174; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs
proactively, and fine-tune applications for parallel performance.
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
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