On Tue, 13 Nov 2018, Charles Steinkuehler wrote:
Date: Tue, 13 Nov 2018 20:12:19 -0600
From: Charles Steinkuehler <char...@steinkuehler.net>
Reply-To: "Enhanced Machine Controller (EMC)"
<emc-users@lists.sourceforge.net>
To: emc-users@lists.sourceforge.net
Subject: Re: [Emc-users] Fun with FPGAs
On 11/13/2018 6:01 AM, Les Newell wrote:
Of course using the generated code in an actual product would be
crazy. It relied heavily on undocumented quirks of the chip. Any
slight change to the chip internal design by the manufacturer is
very likely to break the code. Even production variations would
affect the results.
Which is why their next focus was going to target multiple lots and
temperature ranges. I've worked with FPGA's for 30+ years and what
they did was really cool. While the results don't directly map to a
(theoretically identical) different portion of the chip, note how
rapidly the implementation re-converges to a successful design.
I've also had some experience in pushing FPGA's into "non-standard"
behavior, including using the I/O blocks as delta-sigma ADCs & linear
amplifiers and using internal gates as a ring oscillator. There's a
lot that's possible which you can't do if you obey all the rules! :)
Their design process might not be what you'd want to use for your Next
Big Thing (tm) in today's world, but IMHO it's an intriguing method
with a lot of potential.
--
Charles Steinkuehler
char...@steinkuehler.net
I'm using the simple delta-sigma A-Ds on some new boards using Spartan6 to get
things like potentiometer or thermistor inputs. It works quite well, about 11
bit resolution with 2 Rs and a C per channel. I chose the summing junction
method (1/2 of all LVDS pairs tied 1/2 way up). This has the advantage of
using a fixed common mode so you get full scale range (or greater if you use a
larger resistor on the input vs feedback) but of course the disadvantage of
lower input impedance than the "follower" method.
Peter Wallace
Mesa Electronics
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