On Mon, Oct 19, 2009 at 03:19:36PM +0200, Julian Stoev / Юлиан Стоев wrote: > On Mon, Oct 19, 2009 at 11:36 AM, Florian Pose <[email protected]> wrote: > > I think the phase delay originates from the way, the EtherCAT bus is > > operated. After setting your outputs, the outputs are sent to the > > slaves, while the current slave inputs are queried at the same time(!). > > That means, that the response to your outputs is received at minimum one > > cycle later, that's why it depends on the IO cycle time. > > I am not sure I understand exactly. Do you mean that querying and > actual reading of the slaves should be regarded as two different > samples. The command is given to query. The values become available on > the next time sample?
It just means, that if you send a command to a slave at cycle n, the response to this command is visible in the process data in cycle n + 2, because reading and writing is done together at the beginning of each cycle. -- Best regards, Florian Pose http://etherlab.org _______________________________________________ etherlab-users mailing list [email protected] http://lists.etherlab.org/mailman/listinfo/etherlab-users
