On Mon, Oct 19, 2009 at 5:13 PM, Florian Pose <[email protected]> wrote: > On Mon, Oct 19, 2009 at 03:19:36PM +0200, Julian Stoev / Юлиан Стоев wrote: >> >> I am not sure I understand exactly. Do you mean that querying and >> actual reading of the slaves should be regarded as two different >> samples. The command is given to query. The values become available on >> the next time sample? > > It just means, that if you send a command to a slave at cycle n, the > response to this command is visible in the process data in cycle n + 2, > because reading and writing is done together at the beginning of each > cycle. >
Then again, if I understand correctly, the values should be available at n+1, not n+2? But I think the n+2 is exactly as we detected it. When the loop was working at uniform 1kHz there was a delay ~3ms => 1 ms input delay due to sampling + 2 ms output delays. This is the correct math? This would indicate two options: 1. One has benefit to always run the I/O blocks at the maximum possible sampling rate to minimize such delays. 2. One can make a double quick sample to get minimum output delay and then wait for the normal "long" sampling rate. Such is the approach for example in ADC in hard disk drive firmware. From Simulink point of view the first option is more simple perhaps, but has slight overhead. -- Julian Stoev, PhD. Control Researcher _______________________________________________ etherlab-users mailing list [email protected] http://lists.etherlab.org/mailman/listinfo/etherlab-users
