Hi, First off, my understanding of setting up the DC system is that each slave that wants a Distributed Clock setup calls ecrt_slave_config_dc() specifying the sync0_cycle time and the sync0_shift time (and sync1). The sync0_shift time should be specified as the offset from the nominal start of cycle time, which is specified by the very fist call to ecrt_master_application_time().
Therefore your cycles should always start at: initial_master_application_time + cycle_count * cycle_time Where you start counting cycles as soon as the first ecrt_master_application_time() call is made. I set my sync0_cycle to 1000000 (1ms) and sync0_shift to 500000 (0.5ms). After waking up at the beginning of the cycle I then have 0.5ms to send my EtherCAT frames and have them be processed by all slaves. As to answering "To solve the problem i have to know the systemtime, the next sync0-signal is generated in the slave. Does anybody know if this time is available in a slave with dc-support ?": If the slave has a 64bit DC you should be able to calculate the next sync time as "initial_master_application_time + cycle_count * cycle_time + sync_shift". If the slave has a 32bit DC its more annoying reading the clock but it should be the same calculation, but then remove the top 4 bytes. (You get 4.2 odd seconds before the clock rolls over.) Looking at the ET1100 datasheet document there is a register 0x0990:0x0997 which says it is the "SYNC0 Start Time" - Local copy of System Time (T_localtime + T_offset) (From Section 9.1.5). Regards, Graeme Foot. ________________________________ From: [email protected] [mailto:[email protected]] On Behalf Of WIEGAND Ralf Sent: Wednesday, 2 April 2014 05:23 To: [email protected] Subject: [etherlab-users] DC-Synchronization - Sync signal generation Hello, first of all, thanks to all etherlab-developers for their great job. I have a question about the activation of the sync-signal generation with distributed clocks. I use the ethercatmaster 1.5.1 with the dc-patches from Graeme Foot, kernel 2.6.32.11 with rtai 3.8.1. The application is running over the rtdm-interface and the masterclock is synchronized to the reference clock in slave 1. The slaves are particular developed for us from external companies (FPGA-based designs with Beckhoff IP-Core). The synchronization of the masterclock with the reference clock, like the patches from Graeme Foot, works very well. But i see a constant phase offset between the sync0-signal and the incoming frame (SOF). With every restart of the application the offset is constant during runtime, but with another value. If the value is in a special range, i read the same input pdo values between two cycle times from the slave. To solve the problem i have to know the systemtime, the next sync0-signal is generated in the slave. Does anybody know if this time is available in a slave with dc-support ? Thank you in advance, Ralf Wiegand Ralf Wiegand T: +49 6441 207-410 F: +49 6441 207-387 E: [email protected] <mailto:[email protected]%20> Hexagon Metrology GmbH Siegmund-Hiepe-Str. 2-12 DE-35578 Wetzlar www.hexagonmetrology.de<http://www.hexagonmetrology.de/> | LinkedIn<http://www.linkedin.com/company/hexagon-metrology> | Facebook<http://www.facebook.com/hex.metrology> | Twitter<http://twitter.com/hexmetrology> <www.hexagonmetrology.de> Hauptgeschäftsführer: Holger Fritze Geschäftsführer: Per Holmberg - Arno Seuren - Michael Rosenbruch Amtsgericht Wetzlar, HRB 1201
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