Dear faust users,
please allow me to present a little something to you.
This work originates in the preparation to a test on hardware design at
university. I wanted to model some of the logical circuits in a
graphical environment like Pure Data.
As the solutions I found there were not satifying, I starte playing
around with faust (also to refresh my knowlege of faust for the first IFC ;-)
It turned out, that in Faust it was very straight forward to develop
circuits like a multiplexer, but at the same time it was not very handy
to rewrite the components again and again.
That is why I developed a library.
I know that the idea might seem strange for some of you, and I assume
that the code can be improved at many places. But as I had a lot of fun
preparing it and, as I passed the test with a very satifying grade, I
decided to share it.
I'm curious what people think about it, so am very open to any kind of
feedback.
Find the logic.lib file attached to this mail and in the following
repository:
https://bitbucket.org/g2oo7fy/faust_logic_lib/src/master/
There you will also find aplication patches for Pure Data. Please
consult the README for further information.
With kind regards to everybody,
Bjoern
/////////////////////////////////////////////////////////////////////////
// THE FAUST LOGIC LIBRARY
/////////////////////////////////////////////////////////////////////////
// This library is designed to simplify the modelling of logical circuits
// in Faust.
// Helper Functions:
// A simple helper to negatiate boolian values.
fnot = (1 != _);
// A simple line crosser
x = ((_,_)<:(!,_,_,!));
// And with 3 inputs
and3 = (_,_,_):(_,(_<:(_,_)),_):(&,&):&;
// And leading the original inputs around to the outer outlets
and = (_,_)<:(_,_,_,_):(_,&,_);
// Xor for Faust.
// Might possibly be simplifiable.
fxor = (_<:(_,_)),(_<:(_,_)):(_,((_,_)<:(!,_,_,!)),_):(_ & (_ != 1)), ((_ != 1)
& _): | ;
// 2 Bit decoder for the 4 to 1 Multiplexer
decode24(a,b) =
((a<:(_,fnot)),(b<:(_,fnot))):(_,x,_):(and,_,_):(_,x,x):(_,_,x,_):(_,x,x):(and,and,_):(!,_,_,!,_,_,_):(x,x,_):(_,x,_,_):(&,x,_);
// The small Multiplexer and Demultiplexer Funktions are rather simple
mux21(e0,sel,e1) = (e0,sel,e1):(_,(_<:(fnot,_)),_):(&,&):|;
demux12(e,sel) = (e,sel):((_<:(_,_)),(_<:(_,_)))<:(_,!,!,_,_,!,!,fnot):(|,|);
// The bigger Multiplexer is more complicated and relying on a decoder
mux41 =
(((x,x):(_,x,_):(x,x):(_,x,_)),decode24):(_,_,_,x,_,_,_):(_,_,x,x,_,_):(_,x,x,x,_):(&,&,&,&):(|,|):|;
// A first bistable circuit.
// Check the example svg for documentation.
flipflop(a,b) = ((((| != (1)),_): (_,_)<:(_,!,!,_,_,!):((| != (1)),_)) ~ _
):(!,_);
// This is the common model of a RSflipflop.
// A one-sample-delay is introduced in one of the feedback lines
// To prevent the circuit from running into a run.
RSflipflop(r,s) = (r,s):(_,((_,_)<:(!,_,_,!)),_:(|, |):(fnot,fnot)<:(!,_,_,!))
~ (_',_);
// The latch is a clocked implementation of the RSflipflop
// c is the clock
// a and b are independent values
latch(a,c,b) = (a,c,b)<:(_,_,!,!,_,_) : (&,&) : RSflipflop;
// The Dflipflop is a clocked RSflipflop with the imputs reduced to one.
// The reduction is done with a negation at the R imput.
Dflipflop(d,c) = (d,c):(_,_)<:(_,_,!,!,_,!)<:(_,_,!,!,_,fnot) : (&,&) :
RSflipflop;
// The MasterSlave implementations are stable towards hazards
RSMasterSlave(r,c,s) =
(r,c,s):(_,(_<:(_,_)),_):(_,_,x):(latch,fnot):(_,x):latch;
DMasterSlave(d,c) = (d,c):((_<:(_,fnot)),_):(_,x):RSMasterSlave;
// We need the JKMasterSlave for the implementation of the TMasterSlave
JKMasterSlave(j,c,k) = (k,j):((_,x,_):(((_,fnot):&),&):|,c:DMasterSlave) ~
(_,_);
// The TMasterSlave works as a frequency devider on the clock
// Several TMasterSlaves in a row will serve as a binary counter
TMasterSlave(t,c) = ((t<:(_,_)),c):(_,x):JKMasterSlave;
------------------------------------------------------------------------------
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