On Sat, 2009-05-16 at 21:07 -0700, john wendel wrote: > Intel finally realized that pipeline flushing was the main thing the > processor was doing. The "new" (I7) architecture has fixed this problem, > with very impressive results.
I think you're confusing this with the original Core architecture which more than halved the number of pipeline stages relative to the later models in the Netburst family (up to 31 stages for a late-model Pentium-D, down to just 14 in Core/Core2/Nehalem). The major change with Nehalem is the on-die memory controller and switch from FSB to NUMA multiprocessor organisation using the QuickPath Interconnect (QPI). Regards, Bryn. -- fedora-list mailing list [email protected] To unsubscribe: https://www.redhat.com/mailman/listinfo/fedora-list Guidelines: http://fedoraproject.org/wiki/Communicate/MailingListGuidelines
