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commit af0d56b00e33a6c55d32d743d9e812d73d28a2fb
Author:     Ramiro Polla <[email protected]>
AuthorDate: Fri Jul 17 00:09:47 2026 +0200
Commit:     Ramiro Polla <[email protected]>
CommitDate: Wed Jul 22 14:07:37 2026 +0000

    swscale/aarch64/ops_asmgen: use RasmOp directly when generating masks for 
SWS_UOP_UNPACK
    
    There is no need to pack the vector register usage for this function.
    This change creates holes in the usage of const vector registers, but
    populates the RasmOp const array directly, which will help for the
    implementation of the JIT compiler.
    
    Sponsored-by: Sovereign Tech Fund
    Signed-off-by: Ramiro Polla <[email protected]>
---
 libswscale/aarch64/ops_asmgen.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/libswscale/aarch64/ops_asmgen.c b/libswscale/aarch64/ops_asmgen.c
index 94ee61c725..46e10f80d9 100644
--- a/libswscale/aarch64/ops_asmgen.c
+++ b/libswscale/aarch64/ops_asmgen.c
@@ -626,11 +626,9 @@ static void asmgen_op_unpack(SwsAArch64Context *s, const 
SwsAArch64OpImplParams
     RasmContext *r = s->rctx;
     RasmOp *vl = s->vl;
     RasmOp *vh = s->vh;
-    RasmOp *vt = s->vt;
+    RasmOp *vmask = s->vt;
     RasmOp mask_gpr = a64op_w(s->tmp0);
     uint32_t mask_val[4] = { 0 };
-    uint8_t mask_idx[4] = { 0 };
-    uint8_t cur_vt = 0;
 
     const int offsets[4] = {
         p->par.pack.pattern[3] + p->par.pack.pattern[2] + 
p->par.pack.pattern[1],
@@ -646,7 +644,7 @@ static void asmgen_op_unpack(SwsAArch64Context *s, const 
SwsAArch64OpImplParams
         for (int j = 0; j < 4; j++) {
             if (mask_val[j] == val) {
                 mask_val[i] = mask_val[j];
-                mask_idx[i] = mask_idx[j];
+                vmask[i] = vmask[j];
                 break;
             }
         }
@@ -657,13 +655,13 @@ static void asmgen_op_unpack(SwsAArch64Context *s, const 
SwsAArch64OpImplParams
              * like 10-bit. In those cases, we use mov + dup instead.
              */
             if (val <= 0xff || val == 0xffff) {
-                i_movi(r, vt[cur_vt], IMM(val));
+                i_movi(r, vmask[i], IMM(val));
             } else {
-                i_mov (r, mask_gpr,   IMM(val));
-                i_dup (r, vt[cur_vt], mask_gpr);
+                i_mov (r, mask_gpr, IMM(val));
+                i_dup (r, vmask[i], mask_gpr);
             }
             mask_val[i] = val;
-            mask_idx[i] = cur_vt++;
+            vmask[i] = v_16b(vmask[i]);
         }
     }
 
@@ -684,8 +682,8 @@ static void asmgen_op_unpack(SwsAArch64Context *s, const 
SwsAArch64OpImplParams
     }
 
     /* Apply masks. */
-    LOOP_MASK_BWD      (p, i) { i_and16b(r, vl[i], vl[i], vt[mask_idx[i]]); 
CMTF("vl[%u] &= 0x%x;", i, mask_val[i]); }
-    LOOP_MASK_BWD_VH(s, p, i) { i_and16b(r, vh[i], vh[i], vt[mask_idx[i]]); 
CMTF("vh[%u] &= 0x%x;", i, mask_val[i]); }
+    LOOP_MASK_BWD      (p, i) { i_and16b(r, vl[i], vl[i], vmask[i]); 
CMTF("vl[%u] &= 0x%x;", i, (1u << p->par.pack.pattern[i]) - 1); }
+    LOOP_MASK_BWD_VH(s, p, i) { i_and16b(r, vh[i], vh[i], vmask[i]); 
CMTF("vh[%u] &= 0x%x;", i, (1u << p->par.pack.pattern[i]) - 1); }
 }
 
 /*********************************************************************/

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