08.12.2015 14:53, Dimitry Sibiryakov пишет:
> 08.12.2015 13:39, Vlad Khorsun wrote:
>>     I don't know how to guarantee atomic execution of sequence of two 
>> instructions on Intel HW.
>
>     Don't be confused by pseudocode in function description.

   I'm not confused

>>      You have a proof of course...
>
>     Test program from your link.
>     MSVC assembler:
>
>> ; Line 7
>>      mov     DWORD PTR _cur$[esp+8], 15              ; 0000000fH
>>      push    esi
>> ; Line 9 -         old = _InterlockedOr(&cur, 0xF0);
>>      mov     ecx, 240                                ; 000000f0H
>>      lea     edx, DWORD PTR _cur$[esp+12]
>>      mov     eax, DWORD PTR [edx]
>> $LN3@main:
>>      mov     esi, eax
>>      or      esi, ecx
>>      lock     cmpxchg DWORD PTR [edx], esi
>>      jne     SHORT $LN3@main
>>      mov     DWORD PTR _old$[esp+12], eax
>> ; Line 10 -         _InterlockedOr(&cur, 0xF0);
>>      mov     eax, edx
>>      lock     or      DWORD PTR [eax], ecx
>
>     GCC assembler:
>
>>      movl    $15, 44(%rsp)
>> ;      old = __atomic_fetch_or(&cur, 0xF0, __ATOMIC_SEQ_CST);
>>      movl    44(%rsp), %eax
>> .L2:
>>      movl    %eax, %edx
>>      movl    %eax, %ecx
>>      orb     $-16, %dl
>>      lock cmpxchgl   %edx, 44(%rsp)
>>      jne     .L2
>>      movl    %ecx, 40(%rsp)
>> ;        __atomic_fetch_or(&cur, 0xF0, __ATOMIC_SEQ_CST);
>>      lock orl        $240, 44(%rsp)
>
>

   Do you see the principal difference with Firebird asm code i show ?
Do you see the loop with compare_exchange ?
Do you see the "lock or" operation ?

Do you still have questions ?

Regards,
Vlad

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