On 19.12.2009 04:15, Carl-Daniel Hailfinger wrote: > SuperI/O detection now happens unconditionally and before the chipset > enable. We could run it after chipset enable, but it definitely has to > happen before board enable because the board enable usually accesses the > SuperI/O. > With this patch, it is possible to add a struct superio to the board > enable table for more accurate matching in case subsystem IDs are ambiguous. > This patch focuses on the generic infrastructure aspect and on support > for IT8712F/IT8716F. > > Thanks go to Adrian Glaubitz and Ward Vandewege for testing earlier > versions of this patch. > > Signed-off-by: Carl-Daniel Hailfinger <[email protected]> > Acked-by: Luc Verhaegen <[email protected]> > Acked-by: Adrian Glaubitz <[email protected]> >
Thanks to Ward Vandewege for testing on Gigabyte GA-M57SLI-S4 2.x with IT87 SPI translation. Log follows: flashrom v0.9.1-r811 [...] Vendor ID: GIGABYTE, part ID: m57sli Found ITE SuperI/O, id 8716 Found chipset "NVIDIA MCP55", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Disabling flash write protection for board "GIGABYTE GA-M57SLI-S4"... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled Serial flash pin 29 Serial flash port 0x0820 OK. Calibrating delay loop... 728M loops per second, 100 myus = 0 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0x7a, id2 0x67 [...] Probing for Atmel AT25DF021, 256 KB: RDID returned 0xc2 0x20 0x13. probe_spi_rdid_generic: id1 0xc2, id2 0x2013 Full log at http://coreboot.pastebin.ca/1723867 Committed in r813. Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers." _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
