Patch to enable sis963 southbridge and W83697HF/F SuperIO. DO NOT
APPLY IT, as it needs to be finalised, (tomorrow probably). Please
comment on what else needs to be done (which variables need to be
initialised for example). Yes, it's a bit too verbose, but I'm still
learning hehe. Probe works and detects the flash chip.
Regards,
David
Index: chipset_enable.c
===================================================================
--- chipset_enable.c (revision 1058)
+++ chipset_enable.c (working copy)
@@ -197,6 +197,88 @@
return ret;
}
+static int enable_flash_sis963(struct pci_dev *dev, const char *name)
+{
+#define EFER 0x2E
+#define EFIR EFER
+
+ uint8_t tmp;
+ uint8_t cr2A;
+ uint8_t cr24;
+ int ret = 0;
+
+ /***************************************************************/
+ /* Initialise South-Bridge to enable communication with SuperIO
+ * for ROM access. No supporting documentation, however it works.
+ */
+
+ tmp = pci_read_byte(dev, 0x45);
+ msg_cdbg("\nPCI Read:%x\n", tmp);
+ tmp &= ~0x80;
+ tmp |= 0x40;
+
+ pci_write_byte(dev, 0x45, tmp);
+ tmp = pci_read_byte(dev, 0x45);
+ msg_cdbg("PCI Read:%x\n", tmp);
+ /****************************************************************/
+
+ /* Start communicating with SuperIO chip */
+ w836xx_ext_enter(EFER);
+
+ cr24 = sio_read(EFIR, 0x24);
+ msg_cdbg("read from winbond:%x\n", cr24);
+
+ tmp = sio_read(EFIR, 0x20); //Get Device ID
+ msg_cdbg("winbond device ID:%x\n", tmp);
+
+ tmp = sio_read(EFIR, 0x21); //Get Device Version Number
+ msg_cdbg("winbond version number:%x\n", tmp);
+
+ if (!(cr24 & 0x02)) {
+ msg_cdbg ("Parallel flash detected, size: ");
+
+ switch ((cr24 & 0x30) >> 4) {
+ case 0 : msg_cdbg("1Mbit\n");
+ break;
+ case 1 : msg_cdbg("2Mbit\n");
+ break;
+ case 2 : msg_cdbg("4Mbit\n");
+ break;
+ case 3 : msg_cdbg("ERROR! reserved bits set!\n");
+ ret = -1;
+ }
+
+ cr2A = sio_read(EFIR, 0x2A);
+ msg_cdbg("read from winbond reg_2A:%x\n", cr2A);
+ if ((cr2A & 0xf0) != 0xf0) {
+ msg_cdbg("Flash interface unavailable - GPIO pins are already in use!\n");
+ ret = -1;
+ }
+
+ if (!ret) {
+ if (cr24 & 0x08) {
+ msg_cdbg("MEMW enabled already\n");
+ } else {
+ msg_cdbg("Enabling MEMW\n");
+ sio_write(EFIR, 0x24, (cr24 |= 0x08));
+ if (sio_read(EFIR, 0x24) != cr24) {
+ msg_cdbg("Error, couldn't set MEMW!");
+ ret = -1;
+ }
+ }
+ }
+
+ } else {
+ msg_cdbg ("We have LPC flash, not setting up SuperIO!\n");
+ }
+
+ w836xx_ext_leave(EFER);
+ return ret;
+
+#undef EFIR
+#undef EFER
+}
+
/* Datasheet:
* - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
* - URL: http://www.intel.com/design/intarch/datashts/290562.htm
@@ -1448,6 +1530,7 @@
{0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
{0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
{0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
+ {0x1039, 0x0963, NT, "SiS", "963", enable_flash_sis963},
/* VIA northbridges */
{0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
{0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
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