Works with parallel flash, where there is a W83697HF SuperIO (P4S800-MX motherboard) Not tested in cases where there is LPC flash in the system (if there exists such a setup, though it is supported by the chipset).
Regards, David Borg
Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 1060) +++ chipset_enable.c (working copy) @@ -198,6 +198,98 @@ } /* Datasheet: + * - Name: Winbond W83697HF LPC I/O + * - PDF: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83697hf.pdf + */ +static int enable_flash_superio_W83697HF() +{ +#define EFER 0x2E +#define EFIR EFER + + uint8_t cr26; + uint8_t cr24; + uint8_t cr2A; + int ret = 0; + + w836xx_ext_enter(EFER); + + cr24 = sio_read(EFIR, 0x24); + if (!(cr24 & 0x02)) { + cr2A = sio_read(EFIR, 0x2A); + if ((cr2A & 0xf0) == 0xf0) { + if (!(cr24 & 0x08)) { + + /* Paranoid - Disable register lock (default off) */ + cr26 = sio_read(EFIR, 0x26); + if (cr26 & 0x20) { + sio_write(EFIR, 0x26, (cr26 & (~0x20))); + } + + sio_write(EFIR, 0x24, (cr24 |= 0x08)); + if (sio_read(EFIR, 0x24) != cr24) { + msg_perr("Error: couldn't set MEMW#\n"); + ret = -1; + } + + /* Paranoid - Restore register lock */ + sio_write(EFIR, 0x26, cr26); + + msg_pdbg("Parallel flash size accessible: "); + switch ((cr24 & 0x30) >> 4) { + case 0: + msg_pdbg("1Mbit\n"); + break; + case 1: + msg_pdbg("2Mbit\n"); + break; + case 2: + msg_pdbg("4Mbit\n"); + break; + default: + msg_perr + ("Error: CR24 reserved bits set, must be corrected manually!\n"); + ret = -1; + } + } else { + msg_pdbg("MEMW# already enabled.\n"); + } + } else { + msg_perr + ("Flash interface unavailable - GPIO's in use!\n"); + ret = -1; + } + } else { + msg_pdbg("We have LPC flash, not setting up SuperIO.\n"); + } + + w836xx_ext_leave(EFER); + return ret; + +#undef EFIR +#undef EFER +} + +static int enable_flash_sis963(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + + /***************************************************************/ + /* Initialise South-Bridge to enable communication with SuperIO + * for ROM access. No supporting documentation, however it works. + */ + + tmp = pci_read_byte(dev, 0x45); + tmp &= ~0x80; + tmp |= 0x40; + pci_write_byte(dev, 0x45, tmp); + + /****************************************************************/ + + return enable_flash_superio_W83697HF(); + +} + +/* Datasheet: * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf @@ -1448,6 +1540,7 @@ {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, + {0x1039, 0x0963, NT, "SiS", "963", enable_flash_sis963}, /* VIA northbridges */ {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
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