On Tue, Sep 14, 2010 at 4:59 PM, Carl-Daniel Hailfinger < [email protected]> wrote:
> ICH SPI has the ability to restrict SPI read/write accesses to a given > address range. The low end of the range is configurable by the BIOS (and > by flashrom if the BIOS didn't lock down the flash interface), the high > end of the range is 0xffffff (2^24-1). > This patch checks for an address range restriction and uses the low end > of the allowed range as base for SPI reads. A similar workaround for > REMS/RES opcodes has been committed in r500. > > This fixes read on the Intel D945GCLF mainboard where the stock BIOS > enforces a restricted address range. > Please note that writes need the same fix, but for architectural reasons > that fix will be merged once partial write is available. > > Signed-off-by: Carl-Daniel Hailfinger <[email protected]> > > Index: flashrom-ichspi_read_use_min_addr/spi.c > =================================================================== > --- flashrom-ichspi_read_use_min_addr/spi.c (Revision 1165) > +++ flashrom-ichspi_read_use_min_addr/spi.c (Arbeitskopie) > @@ -22,6 +22,7 @@ > * Contains the generic SPI framework > */ > > +#include <string.h> > #include "flash.h" > #include "flashchips.h" > #include "chipdrivers.h" > @@ -207,6 +208,7 @@ > > int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int > len) > { > + int addrbase = 0; > if (!spi_programmer[spi_controller].read) { > msg_perr("%s called, but SPI read is unsupported on this " > "hardware. Please report a bug at " > @@ -214,7 +216,26 @@ > return 1; > } > > - return spi_programmer[spi_controller].read(flash, buf, start, len); > + /* Check if the chip fits between lowest valid and highest possible > + * address. Highest possible address with the current SPI > implementation > + * means 0xffffff, the highest unsigned 24bit number. > + */ > + addrbase = spi_get_valid_read_addr(); > + if (addrbase + flash->total_size * 1024 > (1 << 24)) { > + msg_perr("Flash chip size exceeds the allowed access > window. "); > + msg_perr("Read will probably fail.\n"); > + /* Try to get the best alignment subject to constraints. */ > + addrbase = (1 << 24) - flash->total_size * 1024; > + } > + /* Check if alignment is native (at least the largest power of two > which > + * is a factor of the mapped size of the chip). > + */ > + if (ffs(flash->total_size * 1024) > (ffs(addrbase) ? : 33)) { > + msg_perr("Flash chip is not aligned natively in the allowed > " > + "access window.\n"); > + msg_perr("Read will probably return garbage.\n"); > + } > + return spi_programmer[spi_controller].read(flash, buf, addrbase + > start, len); > } > > /* > I applied and tested the patch with positive results: http://paste.flashrom.org/view.php?id=79 Acked-by: David Hendricks <[email protected]> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.
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