On 15.09.2010 02:06, David Hendricks wrote: > On Tue, Sep 14, 2010 at 4:59 PM, Carl-Daniel Hailfinger < > [email protected]> wrote: > > >> ICH SPI has the ability to restrict SPI read/write accesses to a given >> address range. The low end of the range is configurable by the BIOS (and >> by flashrom if the BIOS didn't lock down the flash interface), the high >> end of the range is 0xffffff (2^24-1). >> This patch checks for an address range restriction and uses the low end >> of the allowed range as base for SPI reads. A similar workaround for >> REMS/RES opcodes has been committed in r500. >> >> This fixes read on the Intel D945GCLF mainboard where the stock BIOS >> enforces a restricted address range. >> Please note that writes need the same fix, but for architectural reasons >> that fix will be merged once partial write is available. >> >> Signed-off-by: Carl-Daniel Hailfinger <[email protected]> >> > I applied and tested the patch with positive results: > http://paste.flashrom.org/view.php?id=79 > > Acked-by: David Hendricks <[email protected]> >
Thanks for the review and test, committed in r1170. Regards, Carl-Daniel -- http://www.hailfinger.org/ _______________________________________________ flashrom mailing list [email protected] http://www.flashrom.org/mailman/listinfo/flashrom
