Hi David: For flashrom could update BIOS successfully on the Intel Bakerville platform(CPU:SKY-D), we need to add device id to chipset_enables table in the file of"chipset_enables.c", or it will cause below error: WARNING: No chipset found. Flash detection will most likely fail. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically.
So could you please help to add these three device ids to the chipset_enable table and upload to the Github? Attached the changed file. Thanks, Best Regards, Ocean On Wed, Mar 4, 2020 at 2:47 PM Ocean Huang <hah...@celestica.com> wrote: > Thanks a lot. > > On Wed, Mar 4, 2020 at 2:43 PM David Hendricks <dhend...@fb.com> wrote: > >> (Resending to the mailing list) >> ------------------------------ >> *From:* David Hendricks <dhend...@fb.com> >> *Sent:* Monday, March 2, 2020 2:50:24 PM >> *To:* flashrom@flashrom.org <flashrom@flashrom.org>; Ocean Huang < >> hah...@celestica.com> >> *Subject:* Re: [flashrom] Flashrom tool failed on the Intel Bakerville >> platform(CPU:SKY-D) >> >> Hello Ocean, >> At the moment we do not support updating the Intel ME region. You may >> target other regions described by the flash descriptor using the --ifd >> option, for example `flashrom -p internal --ifd -i bios --noverify-all -w >> CBR.1.00.01.bin`*.* >> >> Depending on your use case, another option is to modify the flash >> descriptor to allow the host to write to the ME region. However Intel >> recommends locking the ME region so that reads and writes to the ME region >> from the host are not allowed. >> >> Please also see https://flashrom.org/ME#Suggested_workarounds for >> additional guidance. >> ------------------------------ >> *From:* Ocean Huang via flashrom <flashrom@flashrom.org> >> *Sent:* Wednesday, February 26, 2020 5:20 AM >> *To:* flashrom@flashrom.org <flashrom@flashrom.org> >> *Subject:* [flashrom] Flashrom tool failed on the Intel Bakerville >> platform(CPU:SKY-D) >> >> Hi Vendor: >> >> We have some issue when using flashrom tool update BIOS & ME firmware on >> the Intel Bakeville platform, you can refer to the below error log, could >> you please help give some comments or suggestions about this issue? >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> *[root@localhost flashrom-v1.1]# ./flashrom -p internal -w >> CBR.1.00.01.bin flashrom v1.1 on Linux 3.10.0-957.el7.x86_64 (x86_64) >> flashrom is free software, get the source code at https://flashrom.org >> <https://urldefense.proofpoint.com/v2/url?u=https-3A__flashrom.org&d=DwMFaQ&c=5VD0RTtNlTh3ycd41b3MUw&r=4-bAjA7rj5_lsAnGYQCM_w&m=532SYzVno7CxakMNFHC-ELomxuPqcWKaBcM1kqjV6qc&s=lw-AUImht5ouHueP-_e7nSmbqEDP4RPihF9Y8o5_70A&e=> >> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found >> chipset "Intel C620 Series Chipset Supersku". This chipset is marked as >> untested. If you are using an up-to-date version of flashrom *and* were >> (not) able to successfully update your firmware with it, then please email >> a report to flashrom@flashrom.org <flashrom@flashrom.org> including a >> verbose (-V) log. Thank you! Enabling flash write... SPI Configuration is >> locked down. FREG2: Management Engine region (0x00003000-0x00a15fff) is >> locked. Not all flash regions are freely accessible by flashrom. This is >> most likely due to an active ME. Please see https://flashrom.org/ME >> <https://urldefense.proofpoint.com/v2/url?u=https-3A__flashrom.org_ME&d=DwMFaQ&c=5VD0RTtNlTh3ycd41b3MUw&r=4-bAjA7rj5_lsAnGYQCM_w&m=532SYzVno7CxakMNFHC-ELomxuPqcWKaBcM1kqjV6qc&s=X8yqTjX2TTNy16DkSDCTNXyOc8FAG1Yfn126AxBHqVI&e=> >> for details. At least some flash regions are read protected. You have to >> use a flash layout and include only accessible regions. For write >> operations, you'll additionally need the --noverify-all switch. See manpage >> for more details. Enabling hardware sequencing because some important >> opcode is locked. OK. Found Programmer flash chip "Opaque flash chip" >> (32768 kB, Programmer-specific) mapped at physical address >> 0x0000000000000000. Reading old flash chip contents... Transaction error >> between offset 0x00003000 and 0x0000303f (= 0x00003000 + 63)! FAILED. >> [root@localhost flashrom-v1.1]# ./flashrom -p internal -r 111.bin --ifd -i >> bios flashrom v1.1 on Linux 3.10.0-957.el7.x86_64 (x86_64) flashrom is free >> software, get the source code at https://flashrom.org >> <https://urldefense.proofpoint.com/v2/url?u=https-3A__flashrom.org&d=DwMFaQ&c=5VD0RTtNlTh3ycd41b3MUw&r=4-bAjA7rj5_lsAnGYQCM_w&m=532SYzVno7CxakMNFHC-ELomxuPqcWKaBcM1kqjV6qc&s=lw-AUImht5ouHueP-_e7nSmbqEDP4RPihF9Y8o5_70A&e=> >> Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found >> chipset "Intel C620 Series Chipset Supersku". This chipset is marked as >> untested. If you are using an up-to-date version of flashrom *and* were >> (not) able to successfully update your firmware with it, then please email >> a report to flashrom@flashrom.org <flashrom@flashrom.org> including a >> verbose (-V) log. Thank you! Enabling flash write... SPI Configuration is >> locked down. FREG2: Management Engine region (0x00003000-0x00a15fff) is >> locked. Not all flash regions are freely accessible by flashrom. This is >> most likely due to an active ME. Please see https://flashrom.org/ME >> <https://urldefense.proofpoint.com/v2/url?u=https-3A__flashrom.org_ME&d=DwMFaQ&c=5VD0RTtNlTh3ycd41b3MUw&r=4-bAjA7rj5_lsAnGYQCM_w&m=532SYzVno7CxakMNFHC-ELomxuPqcWKaBcM1kqjV6qc&s=X8yqTjX2TTNy16DkSDCTNXyOc8FAG1Yfn126AxBHqVI&e=> >> for details. At least some flash regions are read protected. You have to >> use a flash layout and include only accessible regions. For write >> operations, you'll additionally need the --noverify-all switch. See manpage >> for more details. Enabling hardware sequencing because some important >> opcode is locked. OK. Found Programmer flash chip "Opaque flash chip" >> (32768 kB, Programmer-specific) mapped at physical address >> 0x0000000000000000. Reading ich descriptor... done. Using region: "bios". >> Reading flash... done.* >> >> -- >> Thanks, >> Best Regards, >> Ocean Huang >> BIOS Engineer >> Celestica(Shanghai) R&D Center, China >> email: hah...@celestica.com >> www.celestica.com >> <https://urldefense.proofpoint.com/v2/url?u=http-3A__www.celestica.com_&d=DwMFaQ&c=5VD0RTtNlTh3ycd41b3MUw&r=4-bAjA7rj5_lsAnGYQCM_w&m=532SYzVno7CxakMNFHC-ELomxuPqcWKaBcM1kqjV6qc&s=ahLKTJPmpgx5K_VNSq96O7Ke4K285bLxzBHr4zcAuv8&e=> >> >> > > > -- > Thanks, > Best Regards, > Ocean Huang > BIOS Engineer > Celestica(Shanghai) R&D Center, China > email: hah...@celestica.com > www.celestica.com > -- Thanks, Best Regards, Ocean Huang BIOS Engineer Celestica(Shanghai) R&D Center, China email: hah...@celestica.com www.celestica.com
chipset_enable.c
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