Phil, Are you saying that you will modify any zero sample by one count to guarantee uniqueness of the sync? Also, it would seem that you would not want to reduce bandwidth by 1/3 to sync every stereo sample. I sync only once every 500 channels in a larger system in the same manner with no confusion.
Richard W5SXD [EMAIL PROTECTED] wrote: (12/01/2005 22:48) > > >Hi Phil, > >I used 48kbps and 16 bit samples to keep things simple for the first test. I >also just used the left audio channel and the blocking version of the >PortAudio code - again a simple first test. > >I was looking at using one of the 2^n A/D states as a flag to indicate the >next data word is say left. Having looked at the output of the Wolfson chip >even with the input shorted you rarely see 0x0000 as data. With a bit of band >noise we will be well above the zero threshold. > >So I am going to start with > ><0x0000><Left_data><Right_data><0x0000><Left_data><Right_data> etc > >Since data delivery using Bulk mode under USB2 is guaranteed I think that >should be sufficient and the loss in dynamic range acceptable in practice. > >Bill suggested that we may not need to send the 0x0000 sync character as often >as shown above given the reliability of the USB2 connection and I will try >reducing its frequency once the above is working. > >I was also thinking of not bothering with testing under PortAudio but going >straight to a PWM D/A converter in the FPGA for the Rx audio. That way I >achieve my goal of removing the sound card and all the Windows drivers - >reading and writing to the Wolfson and D/A's will take but a few lines of code >then. > >Rather than a second A/D converter chip for the mic I was also going to look >at using a PWM ramp feeding one input of a comparator and the mic signal the >other. It may have no advantage over a single chip A/D, given the low cost of >these nowadays, but a fun exercise anyway. > >I only wish that I had time years ago to lean to use FPGAs, they sure open a >whole world of possibilities! > >73s Phil VK6APH > > > >Quoting Philip Covington <[EMAIL PROTECTED]>: > >> Hi Phil, >> >> Good deal, sounds great! I am curious what sampling rate you were >> running the Wolfson chip at and whether your were doing both channels >> or just one for now? Also, what did you decide on for synchronization >> of the audio frames between left and right channels? >> >> 73 de Phil N8VB >> >> On 12/1/05, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: >> > Fellow Xyloeans, >> > >> > Last night I managed to get audio from the Wolfson A/D, via the FPGA and >> FX2 >> > >> > over the USB2 at 480Mbps to the PC and out over PortAudio to the speakers. >> > >> > For some reason PortAudio would hang after a few seconds but it was late >> at >> > night and not the time to start debugging. >> > >> > Having spent some time looking at VHDL I decided to start learning Verilog >> > instead which proved to have a much shorter learning curve. I am just >> > delighted with the Xylo board and how easy it is to program with the free >> > Quartus II software. >> > >> > Next step is to fix the PortAudio bug and get it integrated into the >> SDR1000 >> > software. >> > >> > 73's Phil...VK6APH >> > >> > _______________________________________________ >> > FlexRadio mailing list >> > [email protected] >> > http://mail.flex-radio.biz/mailman/listinfo/flexradio_flex-radio.biz >> > >> >> >> -- >> Philip A Covington >> http://www.philcovington.com >> > > > > >_______________________________________________ >FlexRadio mailing list >[email protected] >http://mail.flex-radio.biz/mailman/listinfo/flexradio_flex-radio.biz
