The FPGA equivalent is to do a syntax check and correct any errors
there, then run a simulation of the input (if using VHDL or Verilog) to
ensure the logic design seems to be OK.
You then compile it, and then run the simulation on the output of the
compiler, because it will sometimes (usually?) infer things from your
statements that you did not intend.
After place and route, you back-annotate and simulate again. Then you
download into the logic, and see if it works! Then you try and
understand why it didn't!!!
I forgot to mention that FPGA software has numerous bugs, and things
that should work don't. Further, things that worked on the last release
often get broken in the push to add features to the new release.
Xilinx and Altera, as the two gorillas in this market, are always
chasing each other, rushing to outdo the other guy. Expect major
releases at least every year, and minor releases/patches every few
months. If you share your source code, include a note to the effect of
the software release you used to compile it so anyone wanting to re-use
it has a "heads up" in case they are suing a different version
(different bugs). If you have to do some weird logic construct to work
around a bug, note it in your source file.
Keep a copy of the software release notes handy. For some vendors, the
list is short. For others, it can run to many tens of pages. And the
list is never complete...
73,
Lyle KK7P
