Sorry I couldn't join in the fun; just too many things going on. TVB's PIC divider is a really elegant hack, and works very well. I'm currently working on a project for TAPR for a universal divider (to take any common frequency standard output and drop it to 1pps) and started out planning to use the PIC design, but changed to a CPLD because that offered more flexibility (or at least a more comprehensible programming model) for what I was trying to do, which has more options than Tom considered.
I suspect that if you're doing something with an FPGA or CPLD anyway, you'll have the gates available in that chip to do the division without having to add another device, so I'd consider that first before adding another block to the system. John ---- Eric Ellison said the following on 01/05/2006 07:14 PM: > Folks > > Missed you on our Teamspeak session last night "It's about time"! > > Had a good discussion amongst a few people working on both the projects > (Xylo) and Flex. Guess the fantastic Texas - USC entertainment got most > others! > > Bob K5KDN is working on a Timebase board, chassis etc and has a Jupiter and > nice 10 mhz Ovenized VCXO interfaced and building a board which will squat > down on the DIP connector on the Jupiter. > > On the Xylo side Bill - KD5TFD published a picture of his breadboard of the > Jupiter interfacing to the Xylo board, which will eventually pass > frequency/phase information back to the PowerSDR software. > > I am looking for more information on anyone who has produced a complete > circuit design published here several months ago by Tom Clark. Based on an > original design by Tom van Baak and enhanced by Tom Clark. > > This is really an inspired design! > > PIC header is published here without permission, however, I did not note a > copyright, and Tom made it available on the Forum several months ago. > > If it uses 10 MHZ this is the way to go! > > ; ---------------------------------------------------------------------- > ; > ; Title: > ; > ; 10 MHz frequency divider > ; > ; Function: > ; > ; This PIC 16c84 program is designed to divide a 10 MHz frequency > ; source down to 1 Hz (1 PPS). > ; > ; Since several extra output pins are available the program creates > ; a total of 9 square wave outputs -- one for each frequency decade > ; from 100 kHz to 0.001 Hz (1000 s). > ; > ; A STOP input and a 1 PPS synchronization input are also provided. > ; Raising the STOP input high stops and resets the divider. The > ; divider resumes on the leading edge of the 1 PPS SYNC input. The > ; 1 PPS output will be synchronized to the 1 PPS SYNC input to less > ; than 1.2 us (three PIC instructions at 10 MHz). > ; > ; The following chip schematic shows the assignment of each pin. > ; > ; ------ ------ > ; 100 kHz <- RA2 |1 --- 18| RA1 -> Red LED > ; Green LED <- RA3 |2 17| RA0 <= Stop input > ; 1PPS SYNC => T0CKI/RA4 |3 16| OSC1/CLKIN <= 10 MHz input > ; +5 VDC -> /MCLR |4 15| OSC2/CLKOUT -- N/C > ; GND -> Vss |5 16C84 14| Vdd <- +5 VDC > ; 10 kHz <- INT/RB0 |6 13| RB7 -> 1000 s > ; 1 kHz <- RB1 |7 12| RB6 -> 100 s > ; 100 Hz <- RB2 |8 11| RB5 -> 10 s > ; 10 Hz <- RB3 |9 10| RB4 -> 1 Hz / 1 PPS > ; --------------- > ; > ; Implementation: > ; > ; To generate a 10 kHz square wave at 50% duty cycle an output pin > ; must be flipped every 50 us (125 instructions at 10 MHz clock). > ; This program does not use TMR0, the pre-scaler, or interrupts. > ; Instead it relies on the fact that given an accurate 10 MHz clock > ; each PIC instruction takes precisely 400 ns and the main loop has > ; been designed to use exactly 125 instructions. > ; > ; The 100 kHz frequency (10 us period) is generated by setting an > ; output pin on and off every 25 cycles. Since 25 is an odd number > ; it is not possible for the PIC to generate this square wave with > ; a 50% duty cycle. Instead a 20% duty cycle (5 cylcles on and 20 > ; cycles off) was chosen for this frequency output. A total of 5 > ; pairs of 100 kHz bit set/clear code are carefully interspersed > ; within the 50 us main loop. > ; > ; Pins RA0 and RA4 are not used to drive a LED. RA4 is a Schmidt > ; trigger input and O.C. output. It is used as the SYNC input. > ; The data sheet says not to toggle RA0 under some conditions so > ; it is used as the STOP input. > ; > ; Version: > ; > ; 1998-Aug-05, Version 4, tvb > ; > ; ---------------------------------------------------------------------- > > ; Using Microhip assembler. > > > > > > > > -----Original Message----- > From: [EMAIL PROTECTED] > [mailto:[EMAIL PROTECTED] On Behalf Of John Ackermann N8UR > Sent: Thursday, January 05, 2006 1:49 PM > To: [EMAIL PROTECTED] > Cc: FlexRadio@flex-radio.biz > Subject: Re: [Flexradio] DIP OCXO for SDR > > Great plan, John. I only had access to the 5052A for a day, so was > pretty limited in what I could do; it's great that you'll be able to > carry things forward. > > The one addition I would suggest is that you duplicate the DDS output > measurements using the 10MHz source as well as the VF oscillator. That > would add to my sketchy info about the effect of the multiplier on phase > noise. > > I was not happy with the results I got, I think due to the way I was > coupling out of the DDS, which was essentially a x1 scope probe with > less-than-perfect grounding. After the fact, I redid the connection > with a 50 ohm series resistor at U1 pin 6 (actually, mounted into a via > on that line) and a short piece of RG-174 feeding a buffer amplifier. I > think something like that will give better results. > > By the way -- I looked at the AD9854 data sheet and it includes several > phase noise plots. From those, you would gather that there is a cost in > using the internal multiplier, but that it doesn't scale with DDS output > frequency. Also, from a quick read you could get the impression that > the phase noise of the reference clock doesn't really matter (within > reason, of course); they show the output phase noise plot without any > reference to the noise of the clock. > > 73, > John > ---- > > [EMAIL PROTECTED] wrote: > >>This is cool. It's great to be able to discuss the nuances of what >>really goes on within our radios. Spreading the word is a very good >>thing. I checked out John's(N8UR) web site and I'm inspired. I have >>an E5052A Signal Source Analyzer setting here and plan to make a few >>measurements. >> >>Here's the plan so far: >> >> i. measure phase noise of a 10MHz crystal >> (it will probably be limited by the E5052A) >> ii. the 200MHz VF1611 >> iii. DDS output with VF1611 as the clock at: >> 1MHz >> 5MHz >> 10MHz >> 50MHz >> >>Anyone have any additional ideas? I'm all ears. >> >>73, >>k2ox >> >> >>-----Original Message----- >>From: richard allen [mailto:[EMAIL PROTECTED] >>Sent: Wednesday, January 04, 2006 5:39 PM >>To: John Ackermann N8UR >>Cc: [EMAIL PROTECTED]; FlexRadio@flex-radio.biz >>Subject: Re: [Flexradio] DIP OCXO for SDR >> >>Gentlemen, >> >>The DDS does Direct Digital Synthesis hence the name. It does not >>divide >>back to anything but runs an phase accumulation engine at 200 MHz (or >>whatever >>the clock rate) that produces output values to the dac at that rate. >> >>No division is performed. >> >>Richard W5SXD >> >>John Ackermann N8UR <[EMAIL PROTECTED]> wrote: >>(01/04/2006 16:09) >> >> >> >>>[EMAIL PROTECTED] wrote: >>> >>> >>>>First of all, any osc multiplied up widens its sidebands >>>>(phase noise) by the multiplication factor and the inverse is >>>>also true. The DDS does a 20X to 200MHz and a divide by 20 to >>>>get back to 10MHz. I guess it's academic at this point how >>>>much jitter is added by the DDS until someone measures it. >>> >>>You're only dividing back to 10MHz if that's the operating frequency. >>>At higher operating frequencies, the division doesn't equal the >>>multiplication (and of course, at lower ones it exceeds it). Measuring >>>the DDS output lets us see the phase noise where it counts, taking into >>>account both multiplication and division, rather than just at the >>>fundamental frequency of the reference. >>> >>> >>> >>>>Second, Rubidium standards are not intended to be used as local >>>>oscillators. They have terrible phase noise. They are intended >>>>to be used in timekeeping. It is their long term drift that >>>>excels, not short term phase noise. >>> >>>Agreed in general -- though there's a wide difference in performance >>>between different types of Rb; some use FM modulation of the xtal, which >>>results in horrible phase noise, while others, like the 5065A, don't. >>>My post wasn't suggesting that you use an Rb as the primary reference. >>>However, the DDS output when driven by 10MHz shows the effect of the >>>multiplication, which is all I was trying to do. My web page also has a >>>plot of the HP 5065A phase noise at 10MHz, so you can see the difference >>>in noise between the raw and multiplied frequencies. >>> >>>John >>> >>> >>> >>>>http://www.febo.com/geekworks/sdr1k/sdr1k_phase/index.html has >>>>screenshots that show the phase noise at the output of the DDS for the >>>>standard 200MHz oscillator, and an HP Rubidium frequency standard at >>>>10MHz multiplied by 20 in the DDS. You can clearly see the phase-noise >>>>hit caused by the multiplication. >>>> >>>>John >>>> >>>>_______________________________________________ >>>>FlexRadio mailing list >>>>FlexRadio@flex-radio.biz >>>>http://mail.flex-radio.biz/mailman/listinfo/flexradio_flex-radio.biz >>>> >>>> >>> >>> >>>_______________________________________________ >>>FlexRadio mailing list >>>FlexRadio@flex-radio.biz >>>http://mail.flex-radio.biz/mailman/listinfo/flexradio_flex-radio.biz >> >> >> >> > > > _______________________________________________ > FlexRadio mailing list > FlexRadio@flex-radio.biz > http://mail.flex-radio.biz/mailman/listinfo/flexradio_flex-radio.biz > > >
