Casey, > [Chuck Thacker chapter]
Note that TinyComputer is a series of designs starting with the one in the first "Steps" report. Just looking at what changed from one to the next is very educational. The recent version in the Beehive brought back some of the flavor of programming in Alto microcode. Then, as now, the processors were far faster than main memory. So starting a memory access was a separate operation from the actual read or write. In the case of Beehive there are queues instead of single registers (inspired by http://www.cs.virginia.edu/~wm/wm.html), which is even nicer. Another important feature of the Alto, that Alan explained in this thread, was the hardware coroutines (inspired by the TX-2). A great advantage of coroutines over interrupts is that the code already has much more context when it starts to execute and so it is done earlier. In the Notetaker this was approximated by having several slower MOS processors sharing a bus and Beehive is a modern version of this. Even so, it would be a cool project to patch the TinyComputers themselves to have hardware coroutines. 16 PCs using distributed memory (64 in a Spartan 6) take up the same FPGA area as a single PC using flip flops, and one block RAM can hold 16 banks of 32 registers (32 bits) each. Merik wrote a very detailed email about SiliconSqueak, so I will just make two more comments about it. The "64 ALU Matrix" he mentioned is an optional coprocessor which has 64 ALUs, each 8 bits wide. By selecting carry options, you can operate on wider values. The ALUs are organized in an 8 by 8 matrix and the registers are shared between neighbors so they can be used for communication. While it is possible to simply compile the Squeak VM for the TinyComputer (http://web.mit.edu/6.173/www/currentsemester/handouts/SoftwareV2.pdf), the idea in SiliconSqueak is to have more layers so the "jump" in each layer is easier for people to follow. These are: 1) Etoys or Scratch tiles 2) Squeak source text 3) bytecodes 4) microcode 5) caches 6) Verilog/Schematics Level 4 has much of the flavor of the macrocode of the first Lisp machines rather than their microcode (which was very Alto-like). This level presents many registers to the programmer that don't really exist, but are actually fancy ways to access the caches (bytecode cache, microcode cache, data cache and stack cache) as can be seen by someone studying level 5. A friend of mine, Etienne Delacroix, has had a lot of success with a project that mixes electronics and arts with both children and university level students. They learn about transistors and build circuits from TTLs recovered from old machines. He would like very much to have an alternative to level 6 where the children would build a SiliconSqueak out of these TTLs and the slightly more modern GALs. I think that is far too ambitious, but would never stand in the way of someone's dream. Perhaps a simpler machine capable of running Little Smalltalk would be more practical? > [OISC] I created a design for one OISC, the SBN (subtract and branch if negative), out of TTLs for Etienne and we wrote some software for it. I should make all that available somewhere. An even more primitive OISC which only copies bytes between two addresses and then unconditionally jumps to a third address is the core of a videgame: http://esoteric.voxelperfect.net/wiki/BytePusher > ["transport triggered" architecture] Back in 1999 I started Merlintec to bring to the market a TTA based Smalltalk machine (ok, Self). The Tachyon processor would have executed four 16 bit wide MOVE instructions on each clock cycle from a 768KB cache. The code in main memory was bytecodes and the compiler translated those to MOVEs on cache misses. There were several insteresting ideas in this project, but I came to the conclusion that I wouldn't be able to write a compiler good enough to take advantage of this hardware on my own. By 2001 the FPGAs had enough internal memory that I could replace the single fast processor with several simpler ones, each with their own caches. One of the functional units in Tachyon implemented PICs (polymorphic inline cache) up to three elements long. > ["Wireworld Computer"] It is very cute. The circuit style of the Wireworld might actually be the way of the future if quantum dots catch on. http://en.wikipedia.org/wiki/Quantum_dot_cellular_automaton http://nd.edu/~qcahome/ Cheers, -- Jecel _______________________________________________ fonc mailing list [email protected] http://vpri.org/mailman/listinfo/fonc
