Re: Zvýraznění PSL ve VHDL a Verilog [60545]

Thu, 25 Apr 2013 02:00:59 -0700 

Diky za rychlou reakci.

Ten kousek kodu co jsem uvedl, kdyz ted na nej zpetne koukam, by nebyly metodou
kterou jsem popsal vysvycene nektere radky, ale stejny PSL kod lze napsat i
nasledovne, a to by se vysvecovalo vse jak ma:

  -- PSL default clock is rising_edge(clk);

  -- PSL sequence request  is {not (req or ack); req};
  -- PSL sequence start_s  is {req[*]; req AND ack};
  -- PSL sequence middle_s is {(req AND ack)[*]};
  -- PSL sequence end_s    is {(not req)[*]; (not req) and (not ack)};
  -- PSL check_handshake : assert always ({request} |=> {start_s; middle_s;
end_s});

  -- PSL illegal_ack : assert never {not req and not ack; not req and ack};

Zdravi Martin Poupa

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