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This thread has been followed for some time. If you are designing an X to ATA-x bridge, the following is true on the ATA side. 1. The device has to be told exactly how many sectors to transfer via the Sector Number register whether it be read or write via either PIO or any DMA. 2. The device will transfer exactly that amount of data unless an error is detected by the device, any kind of reset is issued, or a new command is issued. 3. The device will pause data transfer only between sectors by waiting to post the interrupt and raise DRQ in PIO mode or by de-activating DMAREQ in any DMA mode. I am pretty sure that this is exactly true of an ATAPI device as well, but am not 100% sure all of the details. So if you are designing any X to ATA/ATAPI bridge, your bridge has to be incredibly stupid (meaning that you probably have to be incredibly sharp with your design) or, more likely, your bridge will have to translate commands from the X interface to ATA, buffer data, and handle the specifics of managing each interface. Subscribe/Unsubscribe instructions can be found at www.t13.org.
