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Excusem Moi. I wasn't trying to describe what any host would or would not do. There are many different Hosts who all can act differently. I was pointing out in a big picture sense that before the transfer begins, the Host has to indicate (shall) via the Sector Number register exactly how many sectors are to be transferred and those exact number of sectors are always transferred except under the conditions that I indicated. I wasn't trying to complicate the issue by saying how transfers are paused because that has absolutely no influence whatsoever on the number of sectors to be transferred. At the micro transfer level, it would be more accurate to state that the transfer during DMA's will only pause if the host inactivates DMAACK or the device inactivates DMAREQ under specific timing constraints. On PIO's, the only way that the device can cause a transfer to pause between a sector(on read/write sector) or a block (on multiples) would be by inactivating IORDY, again under specific timing constraints. And that is only good for PIO Modes 3 and greater. The transfer is driven by the Host with either HIOW or HIOR. The drive is not supposed to raise DRQ until it is capable of transferring a complete block or sector for PIO Modes 2 or less. But, again, all the pausing stuff has nothing to do with the number of bytes to be transferred. 1/26/02 2:49:10 PM, "Hale Landis" <[EMAIL PROTECTED]> wrote: >This message is from the T13 list server. > > >On Sat, 26 Jan 2002 10:04:05 -0700, don clay wrote: >>This message is from the T13 list server. >>3. The device will pause data transfer only between sectors by waiting to post >>the interrupt and raise DRQ in PIO mode or by de-activating DMAREQ in any >>DMA mode. > >Ahhh... Not true... There is no requirement (never has been a >requirement) that the device pause or terminate a burst at a sector >boundary. There may be some drives that did that but I don't think it >was or is a common pratice. In MW DMA is was common for host and/or >devices to terminate the burst every 64, 128, 256 words (pick one) so >that some stupid ISA bus motherboards had time to do DRAM memory >refresh cycles. Today I would expect to see Ultra DMA pauses any time >the host or device FIFO full/empty conditions require it and that has >nothing to do with sector boundaries. I would not expect Ultra DMA >burst termination at every sector boundary or even expect that when >burst terminations happen they happen at a sector boundary. > >We must be very careful here... No one should design a host or device >that expects DMA bursts to pause or terminate at sector/block >boundaries. I think this has been one of the things confusing Pat >(Pat is that true?). > > > >*** Hale Landis *** www.ata-atapi.com *** > > > >Subscribe/Unsubscribe instructions can be found at www.t13.org. > Subscribe/Unsubscribe instructions can be found at www.t13.org.
