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> data deficiency or excess
> can already be determined
Of course except that the counts of bytes clocked across the bus get rounded up to the
nearest two bytes, since Ansi SwDma/MwDma/UDma Atapi as yet has no analogue to the
IgnoreWideResidue message of Scsi.
Pat LaVarre x4402
>>> Tony Goodfellow <[EMAIL PROTECTED]> 02/13/02 02:44PM >>>
As I interpret Hales proposal it is only intended to let the Host S/W know
that a data deficiency or excess has occurred. This can already be
determined from the status of bits within the "Bus Master ATA Register" of
the Adapter.
The states are:
Bit nomenclature.
Int = Interrupt bit (2)in the Bus Master ATA Register.
Err = Error bit (1)in the Bus Master ATA Register.
Act = Active bit (0)in the Bus Master ATA Register.
The states are:
Int Err Act
0 0 0 No DMA transfer in progress
0 0 1 DMA transfer in progress and the ATA device has NOT asserted INTRQ.
1 0 0 The device INTRQ and all the data defined by the PRD has transferred
(Normal case).
1 0 1 The device asserted INTRQ and completed the command before the PRD
completes (may be valid for some ATAPI commands).
0 0 0 The adapter has completed the PRD but the drive has not (something wrong).
X 1 X The adapter is having a problem doing the Host DMA transfer (deep water).
Note: If the device sets ERR when it interrupts there are other problems to solve!
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