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I don't know, I wasn't the original designer. Perhaps software wasn't expected to poll on the device status register, but should instead be polling on the ACT bit in the host bus-master device register, or just waiting for the interrupt. So, it shouldn't have mattered, performance-wise. T.E. -----Original Message----- From: Hale Landis [mailto:[EMAIL PROTECTED]] Sent: Wednesday, April 10, 2002 2:22 PM To: [EMAIL PROTECTED] Subject: RE: RE: [t13] UDMA Bursts - Pause versus Termination ... But why do this? From day one of this interface we know that during the execution of a DMA data transfer command a device should have status of BSY=1 (yes, some devices have status of BSY=0 DRQ=1 but that doesn't matter, either status tells the host the device is busy). So why should a host adapter terminate a DMA data burst in progress when the host does a read of one of the device registers? Why not just tell return fake data of 80H and let the DMA data burst continue uninterrupted?
