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On 07 Jan 2004 11:38:33 -0700, Pat LaVarre wrote: >In review, I think I dispute only the point 6 of 8, the claim: >"There can be only 0 or 1 pad bytes in a command's data transfer." Both SFF-8020 and ATA/ATAPI-4 say there may be a single pad byte as the last byte of a PIO or DMA data transfer. Point 6 is one of the very basic rules of ATAPI PIO and DMA data transfers. This implies that the last byte of a PIO DRQ data block or a DMA data burst is immediately followed by the first byte of the next PIO DRQ data block or DMA data burst. There are no 'pad' bytes in between PIO DRQ data blocks or in between DMA data bursts. This has nothing to do with the DMA protocol or the DMA protocol's speed (timing mode). There is a pad byte at the end of the transfer only if the command (the SCSI CDB) describes a SCSI command that requires the transfer of an odd number of bytes. This brings us to the related issue... The host and device must understand every command and how much data every command is expected to transfer and if the last byte is a pad byte. Remember that x86 host side DMA hardware *DOES* *NOT* count the bytes transferred... Only by using the SCSI CDB information can you know how much data a command should have transferred and if there is a pad byte at the end of the transfer. Hale *** Hale Landis *** www.ata-atapi.com ***
