This message is from the T13 list server.
An intelligent host controller could mark up the registers with the error bits on to indicate CRC failure if it so detected one. But one that implements it according to the way the SATA group THINKS parallel ATA emulation should work, would indeed have a problem here. -----Original Message----- From: [EMAIL PROTECTED] To: [EMAIL PROTECTED] Sent: 3/17/2004 7:18 AM Subject: FW: [t13] Checksum implementation issue This message is from the T13 list server. Even in SATA, in a PIO Read using the legacy programming interface there's no good way to report a Data FIS error to software, since it already got the ending status before reading the Data register. The checksum might be useful because of that. --- Rob Elliott, HP Server Storage [EMAIL PROTECTED] > -----Original Message----- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On > Behalf Of [EMAIL PROTECTED] > Sent: Tuesday, March 16, 2004 3:05 PM > To: [EMAIL PROTECTED] > Cc: '[EMAIL PROTECTED]'; [EMAIL PROTECTED]; > [EMAIL PROTECTED]; Pat LaVarre > Subject: RE: [t13] Checksum implementation issue > > > This message is from the T13 list server. > > > > > So why would the SATA checksum that happens as part of the > Data D->H FIS > not > > catch an error in transmission? (Obviously such a CRC > assumes that the > > device got the data into the link layer correctly). > > > > Or am I missing something really obvious here? > > Remember, SATA is not the entire world. > Parallel ATA does not have any CRC-like protection for PIO > mode tranfers. > > > Thank You !!! > ----------------------------------------------------------------- > Jim Hatfield > ATA Interface Firmware & T13 (ATA/ATAPI) Standards Representative > Seagate Technology - PSG > e-mail: [EMAIL PROTECTED] > s-mail: 389 Disc Drive; Longmont, CO 80503 USA > voice: 720-684-2120 > fax : 720-684-2711 > ==================================================== > > > |---------+----------------------------> > | | Mark Overby | > | | <[EMAIL PROTECTED]| > | | om> | > | | Sent by: | > | | [EMAIL PROTECTED]| > | | rg | > | | No Phone Info | > | | Available | > | | | > | | 03/16/2004 03:00 | > | | PM | > | To: "'[EMAIL PROTECTED]'" > <[EMAIL PROTECTED]>, Pat LaVarre | > | <[EMAIL PROTECTED]>, [EMAIL PROTECTED] > | > | cc: > | > | Subject: RE: [t13] Checksum implementation issue > | > > This message is from the T13 list server. > > > So why would the SATA checksum that happens as part of the > Data D->H FIS > not > catch an error in transmission? (Obviously such a CRC assumes that the > device got the data into the link layer correctly). > > Or am I missing something really obvious here? > > -----Original Message----- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On > Behalf Of Andrew > Hill > Sent: Tuesday, March 16, 2004 1:18 PM > To: Pat LaVarre; [EMAIL PROTECTED] > Subject: Re: [t13] Checksum implementation issue > > This message is from the T13 list server. > > > On 16 Mar 2004 11:40:49 -0700, Pat LaVarre <[EMAIL PROTECTED]> wrote: > > [snip] > > > I can add two points: > > > > 1) > > > > Requiring every bit of the hi byte to toggle once or more during the > > read of Identify "word"s would discover the hi byte stuck, > and might be > > compatible with the ATA/PI 5 specification or a small modification > > thereof. > > > > It would be more efficient to use a register bit to indicate > the presence > of a checksum or CRC though, and also provides a method which could be > applied to oether data-providing commands. > Backwards-compatibility can be > maintained too - all that needs to happen is to ensure that > the signiature > A5 isn't present; setting bit 0 to 0 would be enough, and you > could use > the remaining bits for your CRC / checksum. > > > I'm fairly confident that this has been identified an issue with the > current spec. We've also almost got a proposed modification to suit, > although I admit it does need some of the finer points sorting. > > James, is it possible to run this idea past the committee at the next > meeting? > > Best wishes, > > Drew
