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FWIW... those per-register enable bits are impossible to implement on the new FIS-based SATA controllers (i.e. most of the future SATA market).
FIS-based controllers are "all-or-none", and do not have the option of writing only certain ATA shadow registers.
Further, pre-FIS SATA controllers generate a FIS internally to send to the SATA device. On these controllers it is possible for the OS driver to support the per-register enable bits... but the underlying hardware will simply ignore that.
SATA controllers will cache ATA shadow register contents, flushing all registers to the SATA device when the Command or Control register is written.
Jeff
