This message is from the T13 list server.
Jeff
It turns out that during the last T10 meeting I discovered that I
have to pass the transfer length in the CDB. I have a was to do that, but
it is going to cost all the transfer bits. I will have a new command doc
out next week.
------------------------------------------------
Curtis E. Stevens
20511 Lake Forest Dr. #C 214-D
Lake Forest, Ca. 92630
Phone: 949-672-7933
Cell: 949-307-5050
E-Mail: [EMAIL PROTECTED]
-----Original Message-----
From: Jeff Garzik [mailto:[EMAIL PROTECTED]
Sent: Friday, September 24, 2004 3:16 PM
To: Curtis Stevens; [EMAIL PROTECTED]
Subject: comment on T10 ATA-passthru
FWIW... those per-register enable bits are impossible to implement on
the new FIS-based SATA controllers (i.e. most of the future SATA market).
FIS-based controllers are "all-or-none", and do not have the option of
writing only certain ATA shadow registers.
Further, pre-FIS SATA controllers generate a FIS internally to send to
the SATA device. On these controllers it is possible for the OS driver
to support the per-register enable bits... but the underlying hardware
will simply ignore that.
SATA controllers will cache ATA shadow register contents, flushing all
registers to the SATA device when the Command or Control register is
written.
Jeff
