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Hi,
We are designing an ATA controller for an embedded SOC. I had some doubts regarding two points given in the ATA - ATAPI 7 Standard (d1532v1r4b) vol. 2 . I would appreciate
if somebody could help me out in the following issues :
(1) In Parallel Interface timings for Multiword DMA tranfer ( section 12.2.3),
tj { t <sub-script>j }is described as DIOR-/ DIOW- to DMACK hold (min) . [see table 50.]
However, Fig. 70 says, " To terminate the transmission of a data burst, the host shall negate DMACK- within tj after a DIOR- or DIOW- pulse." - which seems to suggest that, tj has
a maximum limit.
This seems to contradict the earlier notion of tj being a DMACK hold time, which has a minimum value. I doubt which one is the case.
(2) In the same section 12.2.3, Fig. 67 says, "The host shall not assert DMACK- or negate both CS0 and CS1 untill the assertion of DMARQ is detected."
However, when the host is idle, it is expected to negate CS0 and CS1 for the PIO protocol.
Doesn't this contradict the above statement, when DMARQ is negated ?
TIA,
Seshadri Kiran Kolluri Design Engineer Neomagic Semiconductor India Pvt. Ltd. Noida, Uttar Pradesh India
