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"Seshadri Kolluri" <[EMAIL PROTECTED]> said:
>We are designing an ATA controller for an embedded SOC. I had some
>doubts regarding two points given in the ATA - ATAPI 7 Standard
>(d1532v1r4b) vol. 2 .
I strongly advise people doing work with parallel ATA (PATA) to avoid
using ATA/ATAPI-7 - use ATA/ATAPI-6.
>(1) In Parallel Interface timings for Multiword DMA tranfer ( section
>12.2.3),
>tj { t <sub-script>j }is described as DIOR-/ DIOW- to DMACK hold (min)
>. [see table 50.]
>However, Fig. 70 says, " To terminate the transmission of a data
>burst, the host shall negate DMACK- within tj after a DIOR- or DIOW-
>pulse." - which seems to suggest that, tj has
>a maximum limit.
>This seems to contradict the earlier notion of tj being a DMACK hold
>time, which has a minimum value. I doubt which one is the case.
The tj minimum time insures that IOR- or IOW- is deassert *before*
DMACK- is deasserted. The statement in Fig. 70 is not worded
correctly - it should probably say that the host shall not negate
DMACK- until after the minimun time tj passed - but I need to look at
ATA/ATAPI-7 Vol 2 to see what Fig 70 is and what it is describing.
>(2) In the same section 12.2.3, Fig. 67 says, "The host shall not
>assert DMACK- or negate both CS0 and CS1 untill the assertion of DMARQ
>is detected."
>However, when the host is idle, it is expected to negate CS0 and CS1 for
>the PIO protocol.
When DMACK- is deasserted the host need not keep the CSx- signals
deasserted. Remember that when DMACK- is deassert the interface is in
"PIO mode" and the CSx- (and DAx) signals could be bouncing around
all the time. The only time a device looks at and uses these signals
is from the leading edge of IOR-/IOW- until the trailing edge of the
same IOx- signal - during this time the host shall not change the
state of the CSx- and DAx signals. It is true that the host shall not
assert DMACK- until after it sees DMARQ asserted and that when it
asserts DMACK- it shall also deassert the CSx- signals.
Hale
*** Hale Landis *** www.ata-atapi.com ***