This message is from the T13 list server.
Thanks to all who replied. You were very helpful.
Matt
-----Original Message-----
From: [EMAIL PROTECTED] on behalf of Eschmann, Michael K
Sent: Thu 10/7/2004 5:03 PM
To: [EMAIL PROTECTED]
Cc:
Subject: RE: [t13] DMA Command Protocol question - What does the host need to
do after sending Command?
Matt,
No, the busy and DRQ wait only happen for a PIO write (and write multiple), so
DMA ca just start the DMA engine and device command and then wait for an interrupt. I
hope this helps.
TTFN, MKE
_____
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Matt Henson
Sent: Thursday, October 07, 2004 2:02 PM
To: [EMAIL PROTECTED]
Subject: [t13] DMA Command Protocol question - What does the host need to do
after sending Command?
Hi,
Iâm designing an ATA controller with UDMA support for an embedded SoC.
Weâve got all of the PIO mode stuff working and are adding UDMA. I have hit a bit
of a roadblock and would appreciate some help.
Iâm looking at ATA-6, d1410r3.
After sending the command (Read DMA or Write DMA) the Host DMA state diagram
seems to require that the host poll the status register and DMARQ line until:
[(BSY=0 & DRQ=1 & DMARQ=1) or (BSY=1 & DRQ=0 & DMARQ=1)]. Is it really
necessary to poll the status register? Can I just turn it over to my UDMA controller,
which will wait for DMARQ=1 or INTRQ=1? If the host needs to read the status register
when entering state HDMA0 from HI4 then does it also need to do it when entering HDMA0
from HDMA1 and the command is not yet complete (ie, DMA burst termination before
command completion)? It seems logical that the host would not have to read the status
register until command completion (successful or otherwise) but perhaps there is more
going on than meets my eye.
TIA,
Matt Henson
Lead Systems Architect, MP3 product group
SigmaTel, Inc.
Austin, TX
512.381.3934
