This message is from the T13 list server.
A follow up message to correct something I said last night...
I said: > Yes, when BSY=0 DRQ=1 the device may change the value of the ERR bit > but that would be dangerous because a host may not see that change > (because it is not common for hosts to read status while in the middle > of reading /writing the data register during PIO data transfers.
Sorry, of course this is not correct... It violates the rules I quoted in the same email: "5.14.5.1 BSY (Busy)... When BSY is cleared to zero, the host has control of the Command Block registers, the device shall:
... 2) not change ERR bit; ..."
Sorry about that... However, if a device did, for some unexplainable reason, want to set the ERR bit to 1 while BSY=0 DRQ=1 then my statement above would apply: hosts don't normally read Status in the middle of a DRQ data block transfer and are not likely to see the change in the ERR bit value.
Hale
--
++ Hale Landis ++ www.ata-atapi.com ++
