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This message refers to the discussion about how BSY and INTRQ operate at the end of a command. This discussion was started privately and then apparently was continued publicly at the last T13 meeting. The discussion was started when I noticed that at least one PATA emulating SATA host controller was not emulating BSY and INTRQ correctly at the end of EXEC DEV DIAG commands when there are two SATA devices configured to appear as devices 0 and 1 on the same ATA channel.
My overall statement is this: For any command, including EXEC DEV DIAG, a device does not assert INTRQ until AFTER it has set BSY=0 status. This is true for ALL times a device might assert INTRQ in any command protocol.
Apparently some people want to break this most basic ATA rules, going back to before ATA-1, and say that even if a host see INTRQ the host may have to additionally wait for BSY=0 status. That is B.S. If a host sees INTRQ and reads the device status and sees BSY=1 the device (or in this case the SATA host controller) has done something very wrong.
If you search ATA/ATAPI-7 you will find many places that say a device sets BSY=0 and then it asserts INTRQ - never the other way. Please see ATA/ATAPI-7 Volume 2 Revision 4b figure 43 "Device bus Idle state diagram". There you will find this text:
<<<DI0: Device_Idle_SI State (selected/INTRQ asserted): This state is
entered when the device has completed the execution of a command protocol with Interrupt Pending and nIEN=0.
When in this state, the device shall have DRQ cleared to zero, INTRQ
asserted, and BSY cleared to zero.
Reading any register except the Status register shall have no effect.
Command register. The host should not write to the Command register at
this time.>>>
For the EXEC DEV DIAG command see:
<<<Transition D0ED3:DI0: When hardware initialization and self-diagnostic testing is completed, the status has been set, and nIEN is cleared to zero, then the device shall clear BSY to zero, assert INTRQ, and make a transition to the DI0: Device_idle_SI state (See Figure 43).>>>
And see these additional similar statements of the same BSY/INTRQ protocol:
DPIOI0:DI0 DPIOI0:DI1 DPIOI2: Data_Ready_INTRQ State DPIOO0:DI0 DP3: Ready_INTRQ State HPD2b:HIO0: DPD1: Receive_Packet State DPD3: Ready_INTRQ State HDMAQ0b:HIO0 DDMAQ0:DI0 DDMAQ0:DI1 DDMAQ0a:DIO0 DDMAQ0a:DIO2
And probably many more places.
It is very clear that a device does not assert INTRQ until AFTER BSY is set to 0.
If a SATA host controller wants to emulate PATA and it does not emulate this BSY/INTRQ protocol then it is (I'm sorry) a BROKEN device.
Hale
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++ Hale Landis ++ www.ata-atapi.com ++
