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This message talks about the BSY, DRQ and ERR bits for PATA.
I have copied text from ATA/ATAPI-7 concerning BSY, DRQ and ERR into this email. That text is marked by ">>". Following each statement/rule I have added my comment concerning the statement/rule.
Summary: As you can see below, everything in these sections of ATA/ATAPI-7 rev 4b vol 1 is correct.
SO....
Question (again): What and why are you trying to change this?
Hale
===BEGIN
>> ------------------- >> 5.14.5.1 BSY (Busy) >> ------------------- >> >> BSY is set to one to indicate that the device is busy. After the >> host has written the Command register the device shall have >> either the BSY bit set to one, or the DRQ bit set to one, until >> command completion or the device has performed a bus release for >> an overlapped command.
This is absolutely correct for all devices at all times.
>> The BSY bit shall be set to one by the device only when one of >> the following events occurs: >> >> after either the negation of RESET- or the setting of the SRST >> to one in the Device Control register;
This is absolutely correct for all devices at all times.
>> 2) after writing the Command register if the DRQ bit is not set >> to one;
This is absolutely correct for all devices at all times. See [NOTE] below.
>> 3) between blocks of a data transfer during PIO data-in commands >> before the DRQ bit is cleared to zero;
This is absolutely correct for all devices at all times.
>> 4) after the transfer of a data block during PIO data-out >> commands before the DRQ bit is cleared to zero;
This is absolutely correct for all devices at all times.
>> 5) during the data transfer of DMA commands either the BSY bit, >> the DRQ bit, or both shall be set to one;
This is absolutely correct for all devices at all times.
>> 6) after the command packet is received during the execution of a >> PACKET command.
This is absolutely correct for all devices at all times. Did all you ATAPI designers see this and implement this?
>> NOTE - The BSY bit may be set to one and then cleared to zero so >> quickly, that host detection of the BSY bit being set to one is >> not certain.
[NOTE] This is what allows a fast device to skip BSY=1 on its way to BSY=0 DRQ=x ERR=x status immediately after the Command register has been written.
>> When BSY is set to one, the device has control of the Command >> Block Registers and:
ABSOULTELY TRUE AT ALL TIMES.
>> 1) a write to a Command Block register by the host shall cause >> indeterminate behavior except for writing DEVICE RESET command;
This is absolutely correct for all devices at all times. See the IOR-/IOW- response tables.
>> 2) a read from a Command Block register by the host may yield >> invalid contents except for the BSY bit itself.
This is absolutely correct for all devices at all times. See the IOR-/IOW- response tables.
>> The BSY bit shall be cleared to zero by the device: >> >> 1) after setting DRQ to one to indicate the device is ready to >> transfer data;
This is absolutely correct for all devices at all times.
>> 2) at command completion;
This is absolutely correct for all devices at all times.
>> 3) upon releasing the bus for an overlapped command;
This is absolutely correct for all devices at all times.
>> 4) when the device is ready to accept commands that do not >> require DRDY during a power-on, hardware or software reset.
This is absolutely correct for all devices at all times.
>> When BSY is cleared to zero, the host has control of the Command >> Block registers, the device shall:
ABSOLUTLEY TRUE AT ALL TIMES.
>> 1) not set DRQ to one;
This is absolutely correct for all devices at all times.
>> 2) not change ERR bit;
This is absolutely correct for all devices at all times.
>> 3) not change the content of any other Command Block register;
This is absolutely correct for all devices at all times.
>> 4) set the SERV bit to one when ready to continue an overlapped >> command that has been bus released.
This is absolutely correct for all devices at all times.
>> 5) clear the DSC bit to zero when an action that uses this bit is >> completed.
This is absolutely correct for all devices at all times.
>> --------------------------- >> 5.14.5.5 DRQ (Data request) >> ---------------------------
>> DRQ indicates that the device is ready to transfer data between >> the host and the device. After the host has written the Command >> register the device shall either set the BSY bit to one or the >> DRQ bit to one, until command completion or the device has >> performed a bus release for an overlapped command.
This is absolutely correct for all devices at all times.
>> The DRQ bit shall be set to one by the device: >> >> 1) when BSY is set to one and data is ready for PIO transfer;
This is absolutely correct for all devices at all times.
>> 2) during the data transfer of DMA commands either the BSY bit, >> the DRQ bit, or both shall be set to one.
This is absolutely correct for all devices at all times.
>> When the DRQ bit is set to one, the host may: >> >> 1) transfer data via PIO mode;
This is absolutely correct for all devices at all times.
>> 2) transfer data via DMA mode if DMARQ and DMACK- are asserted.
This is absolutely correct for all devices at all times.
>> The DRQ bit shall be cleared to zero by the device: >> >> 1) when the last word of the data transfer occurs;
This is absolutely correct for all devices at all times. But better wording could be "when the last word/byte of the current DRQ data block has been transferred".
>> 2) when the last word of the command packet transfer occurs for a >> PACKET command.
This is absolutely correct for all devices at all times. But better wording could be "when the last word of the command packet has been transferred".
>> When the DRQ bit is cleared to zero, the host may: >> >> 1) transfer data via DMA mode if DMARQ and DMACK- are asserted >> and BSY is set to one.
This is absolutely correct for all devices at all times.
>> ---------------------------------- >> 5.14.5.7 ERR / CHK (Error / Check) >> ---------------------------------- >> >> ERR indicates that an error occurred during execution of the >> previous command. For the PACKET and SERVICE commands, this bit >> is defined as CHK and indicates that an exception condition >> exists (See 2.1).
This is absolutely correct for all devices at all times.
>> The ERR bit shall be set to one by the device: >> >> 1) when BSY or DRQ is set to one and an error occurs in the >> executing command.
This is absolutely correct for all devices at all times.
YES! THIS IS CORRECT.
Of course while BSY=1 a device can set ERR=1 (see above). And while BSY=1 the device could set DRQ=1 and ERR=1 but this is strange - the command has failed - there is no data to transfer - why would a device set DRQ=1? However, some devices do this and it is legal. The host should see BSY=0 DRQ=1 ERR=1 the same as BSY=0 ERR=1 (ignore the DRQ bit because the command has failed - there is no data to transfer. But a reset is required to get the device to set BSY=0 DRQ=0 ERR=0.
This strange BSY=0 DRQ=1 ERR=1 thing comes from some really old (like back in 1990) hardware that shipped in large volumes and the tradition may still exist in some hardware shipping today. However, I would agree it should a "not recommended" implementation these days.
>> When the ERR bit is set to one: >> >> 1) the bits in the Error register shall be valid;
This is absolutely correct for all devices at all times.
>> 2) the device shall not change the contents of the following >> registers until a new command has been accepted, the SRST bit is >> set to one or RESET- is asserted: >> >> - Error register; >> - LBA High/Mid/Low registers; >> - Sector Count register; >> - Device register.
This is absolutely correct for all devices at all times.
>> The ERR bit shall be cleared to zero by the device: >> >> 1) when a new command is written to the Command register;
This is absolutely correct for all devices at all times.
>> 2) when the SRST bit is set to one;
This is absolutely correct for all devices at all times.
>> 3) when the RESET- signal is asserted.
This is absolutely correct for all devices at all times.
>> When the ERR bit is cleared to zero at the end of a command the >> content of the Error register shall be ignored by the host.
This is absolutely correct for all devices at all times.
===END
--
++ Hale Landis ++ www.ata-atapi.com ++
