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BSY/INTRQ description update proposal (based on ATA/ATAPI-7 rev 4b).
This proposal makes *NO* changes to the operation of INTRQ. The proposal only documents the proper operation of INTRQ that has existed since before ATA-1.
*** In clause 3.1.54, change the text
from:
3.1.54 Interrupt Pending: In a parallel implementation, an internal state of a device. In this state, the device asserts INTRQ if nIEN is cleared to zero and the device is selected (See Clause 9). In a serial implementation, ...
to (changes in UPPER CASE):
3.1.54 Interrupt Pending: In a parallel implementation, THIS IS an internal state of a device. In this state, the device asserts INTRQ if nIEN is cleared to zero and the device is selected (See Clause 9) AND THE BSY BIT IN THE DEVICE STATUS IS SET TO ZERO. In a serial implementation, ...
Note that I am not addressing the operation of the SATA "I" bit - that I will leave to whatever organization/committee that determines how the SATA interface operates. However, in my opinion a SATA device "shall have I=0 if BSY=1".
*** In clause 8.2.9, add the following one sentence paragraph to the end of the clase:
A device shall not enter the interupt pending state when the device status has the BSY bit set to one.
Hale
--
++ Hale Landis ++ www.ata-atapi.com ++
