[t13] Query related to Spread Spectrum Clocking in Serial ATA PHY Gen 1

[maruthisudheer.nalam]

Hi   I am working on the Gen1 Serial ATA PHY and I require a clarification regarding Spread Spectrum Clocking (SSC) implementation. In Table 14 (pg: 85) of “Serial ATA: High Speed Serialized AT Attachment, Specification Sheet, Revision 1.0a, 7 January 2003” the peak reduction at 7th Harmonic is mentioned as 7 dB for clock frequencies 66 MHz and 75 MHz.   If the Serial ATA Gen 1 has a data rate of 1.5 Gbps and requires a clock frequency of 1.5 GHz, why the spectral peak reductions are mentioned for 66 MHz and 75 MHz clock frequency rather than for 1.5 GHz clock frequency? Is there any formula to calculate the amount of possible peak reduction for 1.5 GHz clock with the given data?   I would be glad if someone can throw light on this issue.   Thank You Sudheer Confidentiality Notice The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain confidential or privileged information. If you are not the intended recipient, please notify the sender at Wipro or [EMAIL PROTECTED] immediately and destroy all copies of this message and any attachments.