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Hi, The device goes from DPIOO2:Receive_data to DPIOO0:PIO_out after the R_ERR is sent to the host. At this point, arc 2 of DPIOO0:PIO_out that transitions to DPIOO3:Send_status would be taken since the command was aborted due to error. In DPIOO3:Send_status, a Register FIS would be sent where in the Status register BSY=0, DRQ=0, and ERR=1. In the Error register, the ABRT and ICRC bits should be set per updates that are included in latest drafts of ATA8-ACS. Updates have been made to the Interface CRC description to allow ICRC reporting for MWDMA and PIO, and additional notes have been added to the Error Outputs for all PIO data-in and PIO data-out commands to allow this. Note that irregardless of the error, the next step by the host is to send the Register FIS since he only is doing a 1 sector transfer. For future inquiries specific to the Serial ATA documentation within SATA-IO, might I suggest submitting the questions to that forum to ensure those folks address the issues & concerns raised with the technical content which they own. This can be done in several ways: 1) if you or someone you know is involved in the technical forums the questions can be brought forward, or 2) there are areas on the SATA-IO website where inquiries (technical or not) can be submitted to an email address when then are appropriately reviewed and responded to. Regards, Brian Dees -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Alexander Krebs Sent: Wednesday, December 14, 2005 4:51 AM To: [email protected] Subject: [t13] SATA PIO data-out with Data FIS error This message is from the T13 list server. Hi all, I have a question on the device PIO data-out command protocol. I'm using SATA-IO's SATA spec 2.5. Let's assume the following sequence: 1 Software programs task file registers to transfer 1 sector to device using PIO 2 HBA sends Register FIS with command information to device 3 Device sends PIO Setup FIS to host, Status = 0x48, E_Status = 0xc0 4 Seeing BSY == 0 and DRQ == 1, software writes one sector to the Data register 5 HBA sends Data FIS to device, some error corrupts the FIS and it is answered with R_ERR by the device 6 HBA places E_Status in Status register (BSY still 1) because byte count for DRQ block is reached (HT_PIOOTrans2->HT_PIOEnd) And now my question: Is the device required to transition from DPIOO2: Receive_Data to DPIOO3: Send_Status and send a Register FIS (with BSY = 0 and ERR = 1) to the host? From how I interpret the spec, I assume yes. Could anybody please second or oppose? Otherwise, BSY would remain 1 and software would need to detect a time-out. Thanks in advance, Alex.
