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Dear all, In clause 8.27.5.1, page 170 of ATA/ATAPI-6, it says the DRQ bit shall be set to one in the data transmission condition of normal outputs for READ DMA QUEUED command. However, in clause 8.28.5.1, page 174 of ATA/ATAPI-6, DRQ is said to be zero for READ DMA QUEUED EXT command. For the READ DMA QUEUED EXT command, the normal outputs for bus release condition shall have DRQ cleared to zero as shown in clause 8.28.5.2 on page 175. When the host reads back the Status register from the delivery of READ DMA QUEUED EXT command, how can the host determines the device is at the condition of data transmission or bus release? In clause 7.15.6.5 on apge 73, it indicates that DRQ means Data request, therefore, when the device has already prepared data for transfer after the READ DMA QUEUED EXT command, I think DRQ bit shall be set one to indicate the "data request". Moreover, in figure 36 on page 349, DRQ=1 if the state transits to DDMAQ1:Transfer_Data at device, and in figure 35 on page 347, DRQ=1 is the necessary condition for the state transition to HDMAQ1:Transfer_Data at host. Therefore, I think the DRQ bit shall be set to one in clause 8.28.5.1 on page 174 for the data transmission condition of READ DMA QUEUED EXT command such that the host could differentiate the condition as either data transmission or bus release if both SERV and ERR bits are returned 0. The same bug occurs for WRITE DMA QUEUED EXT command, too. Could anyone correct or confirm my perspectives? Thank you! Best regards, Kepler
