This message is from the T13 list server.
kepler wrote:
This message is from the T13 list server. In clause 8.27.5.1, page 170 of ATA/ATAPI-6, it says the DRQ bit shall be set to one in the data transmission condition of normal outputs for READ DMA QUEUED command. However, in clause 8.28.5.1, page 174 of ATA/ATAPI-6, DRQ is said to be zero for READ DMA QUEUED EXT command.
Again, the READ/WRITE DMA QUEUED EXT command descriptions are incorrect. Use the READ/WRITE DMA QUEUED command descriptions - they appear to be correct (and are the same except for the LBA28/LBA48 difference in command parameters). And again, ATA/ATAPI-7 has the same 'errors' in the READ/WRITE DMA QUEUED EXT command descriptions.
For the READ DMA QUEUED EXT command, the normal outputs for bus release condition shall have DRQ cleared to zero as shown in clause 8.28.5.2 on page 175. When the host reads back the Status register from the delivery of READ DMA QUEUED EXT command, how can the host determines the device is at the condition of data transmission or bus release?
For the O/Q command when a device has status of BSY=0 DRQ=0 it could mean command completion or bus release - if it is command completion REL=0, if bus release REL=1.
In clause 7.15.6.5 on apge 73, it indicates that DRQ means Data request, therefore, when the device has already prepared data for transfer after the READ DMA QUEUED EXT command, I think DRQ bit shall be set one to indicate the "data request". Moreover, in figure 36 on page 349, DRQ=1 if the state transits to DDMAQ1:Transfer_Data at device, and in figure 35 on page 347, DRQ=1 is the necessary condition for the state transition to HDMAQ1:Transfer_Data at host.
Clause 7.15.6.5 (ATA/ATAPI-6) may not have the best wording for how DRQ is used by the DMA QUEUED commands. Note that these commands must use DRQ=1 so that the host can read the Command Block registers especially so the host can read the Sector Count register. However, please note that DRQ=1 is 'normally' used only by PIO Data In/Out commands and only when the device expects the host to read/write the Data register. This use of DRQ=1 during a DMA command is 'unusual' but required so the host can read the Command Block registers (long story here but it has to do with setting up the host side DMA engine for these commands).
Therefore, I think the DRQ bit shall be set to one in clause 8.28.5.1 on page 174 for the data transmission condition of READ DMA QUEUED EXT command such that the host could differentiate the condition as either data transmission or bus release if both SERV and ERR bits are returned 0. The same bug occurs for WRITE DMA QUEUED EXT command, too.
Yes, again the READ (and WRITE) DMA QUEUED EXT command descriptions have a number of incorrect statements. Again use the R/W DMA QUEUED command descriptions (in both ATA/ATAPI-6 and ATA/ATAPI-7).
Hale -- ++ Hale Landis ++ [EMAIL PROTECTED] ++
