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Aravind.Navada said: > This message is from the T13 list server. > I am with Analog Devices Inc, Wilmington, MA. There are a few > clarifications regarding the standard that I would like to pose from the > point of a view of a ATA/ATAPI host controller. > > #1 When a DMA transfer (both multi-word and UDMA) is terminated by the > host before all data is transferred, what would be the behavior of the > device ? When you say "terminated by the host" do you mean: a) the host forced burst terminate for some reason other than the host thinks the command is completed, or b) the host thinks the command is completed and all the data has been transferred? Case a) is common - host controllers force burst termination all the time based on host internal bus activities (such as how busy an x86's PCI bus is doing other data movements). Case b) could indicate an error in the host software because the host side DMA engine and the device where not programmed to transfer the same number of bytes. If the device thinks the DMA command's data transfer is not completed, then a) for MultiWord DMA the device will reassert DMARQ or keep DMARQ asserted because it wants the host to transfer more data, and b) for UltraDMA the device will reassert DMARQ (unlike MultiWord DMA, DMARQ is always deasserted as part of UltraDMA burst termination). > Is the device REQUIRED to keep its DMARQ signal high for the > host to get back to complete the transfer ? If the device wants to transfer more data then the device will reassert DMARQ (but for MultiWord DMA the device may or may not have deasserted DMARQ if/when the host forced burst termination). > The standard is ambiguous on > this. Can the behavior be different for different devices ? Yes. MultiWord DMA permits several valid implementations regarding how a device handles the DMARQ signal between DMA bursts. UltraDMA is more restrictive in how DMARQ must be handled. > We have a case in our host implementation where a termination might be > needed during a transfer of a sector (say after 128 ATA words but before > the 256 words for a sector). Does the device keep the DRQ = 1 and BSY = > 0 and continue the transfer ? A device should not have status of BSY=0 DRQ=1 during the execution of a DMA command. DRQ is traditionally and normally used only by PIO data transfer commands and BSY=0 DRQ=1 means the device expects the host to transfer data by reading/writing the Data register (there is no Data register during DMA commmands). However, note that BSY=0 DRQ=1 status is used by the old R/W DMA QUEUED commands and by the PACKET command but not because the device expects the host to access the Data register but so that the host can read the 'command tag' and other state information from the Sector Count (ATAPI Interrupt Reason) register. The ATA/ATAPI device side DMA diagram shows that both BSY=1 and BSY=0 DRQ=1 status is valid for DMA commands only because there are many older ATA/ATAPI devices that used BSY=0 DRQ=1 status during DMA commands even though it had no pratical meaning - both status values indicate 'command in progress' but during a DMA command status of BSY=0 DRQ=1 does not mean the host should attempt accesses to the Data register! > In section 9.7 of the spec, the device > state machine doesnt indicate WHEN the device makes the DDMA0:DDMA1 > transition after a burst has been terminated. DDMA0:DDMA1 happens when the device wants more data transferred and the device is ready to transfer that data. > #2 When does the ATA device tristate/release the data bus on a DMA > (Multiword DMA as well as Ultra DMA) read transfer ? For MultiWord DMA see the tF and tH timing values in the MultiWord signal timing diagrams. For UltraDMA most likely the sender of the data does not actually tristate the data bus until the end of the DMA burst, see the tAZ timing value in the UltraDMA signal timing diagrams. > Is it after the > termination of the transfer or is it after every data word (Does the > device drive the data bus only during Tg and Tf in Multiword DMA and > Tdvs and Tdvh in UDMA) ? The waveforms in the ATA standard seem to > suggest that the device releases the data bus only when a transfer is > terminated/ended. Can you please confirm ? MultiWord DMA is just like PIO - the device may tristate the data bus between each word. But this is not required for PIO (when the host holds the 'address signals' stable during the accesses to the Data register) and not required for MultiWord DMA until burst termination (when the host deasserts DMACK so that the address signals are once again valid). UltraDMA does not require the sender of the data to tristate between words either. In all cases (PIO, MultiWord and Ultra DMA, tristating the data bus between words could really slow things down. See note 4 in the PIO Data Transfer timing diagram. Hale -- Hale Landis -- [EMAIL PROTECTED]
