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Hi,
I am with Analog Devices Inc, Wilmington, MA. There are a few
clarifications regarding the standard that I would like to pose from the
point of a view of a ATA/ATAPI host controller.
#1 When a DMA transfer (both multi-word and UDMA) is terminated by the
host before all data is transferred, what would be the behavior of the
device ? Is the device REQUIRED to keep its DMARQ signal high for the
host to get back to complete the transfer ? The standard is ambiguous on
this. Can the behavior be different for different devices ?
We have a case in our host implementation where a termination might be
needed during a transfer of a sector (say after 128 ATA words but before
the 256 words for a sector). Does the device keep the DRQ = 1 and BSY =
0 and continue the transfer ? In section 9.7 of the spec, the device
state machine doesnt indicate WHEN the device makes the DDMA0:DDMA1
transition after a burst has been terminated.
#2 When does the ATA device tristate/release the data bus on a DMA
(Multiword DMA as well as Ultra DMA) read transfer ? Is it after the
termination of the transfer or is it after every data word (Does the
device drive the data bus only during Tg and Tf in Multiword DMA and
Tdvs and Tdvh in UDMA) ? The waveforms in the ATA standard seem to
suggest that the device releases the data bus only when a transfer is
terminated/ended. Can you please confirm ?
Regards
-- Aravind
