Hi Geoff,
thanks for your answer, is just I was wandering what would be the strategy
for �joining� internal planes?
Regards,
Dan Klepper
-----Original Message-----
From: Geoff Harland [mailto:[EMAIL PROTECTED]]
Sent: Monday, 28 May 2001 11:38
To: Protel EDA Forum
Subject: Re: [PEDA] power planes
We are trying to find a solution, to, actually a very common design
challenge: On our PCB we have different potentials eg: GND, A-GND and
PSU-GND, and need to run those planes separate but to join them together
in a certain point called Star Point (ex: a larger pad between plane and a
thick track, or a gap between multiple planes).
Problems:
1. Starting in the Schematic DRC, we'll record a violation by trying to join
different nets together.
2. Then in the PCB we can run the planes separate and then by forcing a
violation, manually to join them. This means to relay in not forgetting to
do so.
But what we would like to know, is if in Protel (or other) is there a way in
using this option of star point (by linking of different nets together)
without causing any upsets in the checking's programmes, and still being
able to use the net list generated from SCH Editor. The PCB pakage should
then produce a warning or an error indicating the nets have not been joined
by copper.
Dan
[EMAIL PROTECTED]
One good way, first described by Abdulrahman Lomax, is to define a component
whose footprint consists of (just) two retangular pads. The dimensions and
locations of these pads are such that there should be a *very small* gap
between these, to wit 2 microinches (2 * 10**-6 inches) if I recall
correctly. Such a component should be inserted in the PCB file, and a
corresponding component should *also* be added to the *schematic* file. The
trick is to then define a Design Rule (in the PCB file) which is specific to
that component, in which a clearance of 1 microinch between that component's
pin 1 and pin 2 needs to be achieved. (And because the gap betwen these pads
is 2 micoinches, that requirement *is* complied with.) One of the pins is
assigned to one net, while another pin is assigned to the other net. That
way, these nets are connected in a *controlled manner*, to wit via (just)
the *very small* gap that separates those pins.
This technique works in practice, because when the PCB manufacturer produces
a PCB file from the Gerber files which are produced from the PCB file, the
gap is so small that it will be bridged by copper; the two nets concerned
are thus connected as desired (and *only* in the vicinity of the pads
concerned, which is what is desired in the circumstances).
Doing things this way means that the implementation is *also* documented by
the schematic file, and it is not necessary to tolerate DRC errors (in the
PCB file), or to add any shorting tracks *after* running a DRC check (and
before producing Gerber files).
Given that it is currently Sunday in the USA, it is not certain that
Abdulrahman Lomax will also answer your question (in the near future). But I
am fairly sure that if I have mis-stated any aspect of his procedure (or
left some detail out), then he will provide a follow-up response.
I have used this procedure myself (in place of an inferior procedure
involving Mechanical layers, which I used to use, before becoming aware of
this technique). It really does work as described.
Regards,
Geoff Harland.
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