I'm reading
http://4pcb.com/capabilities.htm
and it claims that inner-layer clearances must be at least 15 mil
while outer-layer clearances must be at least 7 mil.
How to I set Design Rules in the PWB editor to enforce this ? (or a slightly
more conservative 16 and 8) ?
I haven't had any coffee yet today, so I'm probably missing something really
simple ...
--
David Cary
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