Hi, most of the demo stuff for vhdl is designed for 16-bit
the steps you would have to take to make the whole thing 8-bit would be 1.) adapt vhdl-foxbone code 2.) kernel drivers (linux-2.6/drivers/fox-vhdl/foxbone*) i can give you advise with the kernel side, for the vhdl stuff, you are probably best of asking roberto. the other thing is, that the 8-bit that you do not want to use, would have to be put into input on the fpga. however, you are aware, that there is a vhdl module, that lets you use the fpgas pins as gpio ? this will be slower than std gpio though.. what application are you trying to make ? John --- In [email protected], "andrea.maccaferri" <[EMAIL PROTECTED]> wrote: > > I'm just waiting for a FOX VHDL dev kit to do some test, > meantime I just wonder me if it will be possible to implement > a reduced FOXBONE protocol version, enabling use of only 8 bit bus, > this could help in application where I/O have to be saved. > 256 register may be enought for many applications, the same for > register size. > I know that you have designed it to assign different address to > different function, so a reduced addressing schema could be a problem, > but this could be resolved writing address in 2 phase, first 8 bit > at address_write rising edge and second 8 bit of address at falling > edge. > > The main problem that I see at the moment is foxbone release > version number that actually is described by 16 bit. > > Let me know what do you think about and if anybody else has the same > requirement. > > Andrea >
