ok.... the foxbone code will work for a 8-bit device with out any problems.
just use only addresses 0-255 and do a &0xff on the result you get when writing data. simple as that, no changes need to be made to the driver code. The release registers are not really used for anything inside the kernel, or at least i cannot remeber doing anything like that. so they will just be set to a random value... John --- In [email protected], "andrea.maccaferri" <[EMAIL PROTECTED]> wrote: > > I have just ordered a fox vhdl kit to do some tests, > but my final application will only use the fox board to control > by network a data acquisition system based on a xilinx fpga. > The problem to transfer data to/from the xilinx chip is the same, > as in foxvhdl, so I think to implement the foxbone architecture inside > the xilinx chip. > Unfortunally I'm quite short on I/O on fpga, but I just need about 8 > register of 8 bit each one. > This is the reason to propose a reduced FOXBONE that could be used by > the standard kernel driver maintained by community. > > Andrea > > > --- In [email protected], "blogic79" <john@> wrote: > > > > Hi, > > > > most of the demo stuff for vhdl is designed for 16-bit > > > > the steps you would have to take to make the whole thing 8-bit > would be > > 1.) adapt vhdl-foxbone code > > 2.) kernel drivers (linux-2.6/drivers/fox-vhdl/foxbone*) > > > > i can give you advise with the kernel side, for the vhdl stuff, you > > are probably best of asking roberto. > > > > the other thing is, that the 8-bit that you do not want to use, > would > > have to be put into input on the fpga. > > > > however, you are aware, that there is a vhdl module, that lets you > use > > the fpgas pins as gpio ? this will be slower than std gpio though.. > > > > what application are you trying to make ? > > > > John > > > > --- In [email protected], "andrea.maccaferri" > > <a.maccaferri@> wrote: > > > > > > I'm just waiting for a FOX VHDL dev kit to do some test, > > > meantime I just wonder me if it will be possible to implement > > > a reduced FOXBONE protocol version, enabling use of only 8 bit > bus, > > > this could help in application where I/O have to be saved. > > > 256 register may be enought for many applications, the same for > > > register size. > > > I know that you have designed it to assign different address to > > > different function, so a reduced addressing schema could be a > problem, > > > but this could be resolved writing address in 2 phase, first 8 bit > > > at address_write rising edge and second 8 bit of address at > falling > > > edge. > > > > > > The main problem that I see at the moment is foxbone release > > > version number that actually is described by 16 bit. > > > > > > Let me know what do you think about and if anybody else has the > same > > > requirement. > > > > > > Andrea > > > > > >
