I'm trying to use the foxvhdl board & foxboard alltoghether. I need to use quite all j3 pin as input to fpga. I need to built 28 counters to count input pulse during a sample time programmable. So I have a 5Mhz clock input as clock for my sample interval, a synch 1hz pulse to synchronize my internal time base, and 28 input signal to be counted, so I'm quite short on input available. All work correct except that pin JP3.3 and JP3.4 looks as there is an electrical conflict on them and input counted on them are wrong, sometimes more then expected, sometime less then expected. Looking to electrical schematics of foxvhdl it looks that a conection to PB4, PB6 and PB7 is present on JP3.3, JP3.4 and JP3.5. Which is the function of this connection ? May I remove R30, R34 and R33 to remove the conflict?
best regards Andrea Maccaferri
