Many Thanks, your suggestion work very well, now I wander me if is it possible to change the I/O input output setting using the sdk at the fimage compile time and how to do it ?
best regards --- In [email protected], Roberto Asquini <[EMAIL PROTECTED]> wrote: > > Hi Andrea, > > the meaning of the connection between PB4, PB6 and PB7 and three FPGA > pins and J3 is to have more flexibility if you need to have more > auxiliary lines from the Fox and the FPGA . You can avoid to pull out > R30, R33 and R34 (that would be quite irreversible since the little size > of those resistors in package 0402) simply programming in input the PB4, > PB6 and PB7 lines. > > If you run the command "readbits" from the Fox console or telnet or ssh > session you can see an output like this: > 111XXX1X XX00XXX1 XXXXXXX11111111101101111XX111111 > > The mid part: XX00XXX1 is the input from portB where 1 is PB0. So you > can see that in my board PB4 is an input, PB6 and PB7 are output since > they show a "X" as input. > > All you have to do is to program in input those lines with simple IOCTLs > with a simple program like this: > > #include "stdio.h" > #include "stdlib.h" > #include "unistd.h" > #include "sys/ioctl.h" > #include "fcntl.h" > #include "linux/gpio_syscalls.h" > > int main(int argc, char **argv) { > > // set PB4 as input > gpiosetdir(PORTB, DIRIN, PB4); > > // set PB6 as input > gpiosetdir(PORTB, DIRIN, PB6); > > // set PB7 as input > gpiosetdir(PORTB, DIRIN, PB7); > > return(0); > } > > > After the program run the command readbits will show the lines PB4, PB6 > and PB7 as inputs with their actual logic values instead of "X". > > Please tell me if you need more advise on that. > > Roberto Asquini > > > > andrea.maccaferri ha scritto: > > > > I'm trying to use the foxvhdl board & foxboard alltoghether. > > I need to use quite all j3 pin as input to fpga. > > I need to built 28 counters to count input pulse during > > a sample time programmable. > > So I have a 5Mhz clock input as clock for my sample interval, > > a synch 1hz pulse to synchronize my internal time base, and 28 input > > signal to be counted, so I'm quite short on input available. > > All work correct except that pin JP3.3 and JP3.4 looks as there is > > an electrical conflict on them and input counted on them are wrong, > > sometimes more then expected, sometime less then expected. > > Looking to electrical schematics of foxvhdl it looks that a conection > > to PB4, PB6 and PB7 is present on JP3.3, JP3.4 and JP3.5. > > Which is the function of this connection ? > > May I remove R30, R34 and R33 to remove the conflict? > > > > best regards > > > > Andrea Maccaferri > > > > > > > > __________ Informazione NOD32 2187 (20070413) __________ > > > > Questo messaggio รจ stato controllato dal Sistema Antivirus NOD32 > > http://www.nod32.it > > > -- > Roberto Asquini > Acme Systems srl > [EMAIL PROTECTED] > http://www.acmesystems.it >
