Perhaps someone can help me with interrupts on riscv32:
I have now changed the compiler to create proper interrupt routines, all
used registers are saved on stack, so far so good:
MTIP_ISR:
.Lc2:
sw x1,-4(x2)
sw x8,-8(x2)
sw x10,-12(x2)
sw x11,-16(x2)
addi x8,x2,0
*addi x2,x2,-68*
.La1:
auipc x10,%pcrel_hi(U_$P$TEST_$$_SYSTICKCOUNTER)
addi x10,x10,%pcrel_lo(.La1)
lw x11,0(x10)
addi x11,x11,1
sw x11,0(x10)
*addi x2,x8,0*
lw x11,-16(x2)
lw x10,-12(x2)
lw x8,-8(x2)
lw x1,-4(x2)
mret
but I am a little uncertain with stackframe size.
For mipsel I did tweak function
trv32procinfo.calc_stackframe_size:longint in cpupi.pas to increase the
stackframe size so that the stackframe can hold all registers in worst
case, when using interrupts also temp registers must be saved on stack
when they are used.
but in risc32 this function looks a lot different, I cannot see any
handling of int registers, only float seems to be covered.
calc_stackframe size is used to calc localsize in g_proc_exit, to better
understand if I have covered all cases, how can I make localsize var > 0?
From the generated code I see that in my example code localsize must
have been <=0. I tried adding local vars to the interrupt routine but
this did not change the generated code, only stackframe size was
adjusted as expected so localsize must still have been <=0
Can you please point me in the right direction?
Thank you,
Michael
Interrupt Routine with two local vars:
MTIP_ISR:
.Lc2:
sw x1,-4(x2)
sw x8,-8(x2)
sw x10,-12(x2)
sw x11,-16(x2)
addi x8,x2,0
*addi x2,x2,-76*
.La1:
auipc x10,%pcrel_hi(U_$P$TEST_$$_SYSTICKCOUNTER)
addi x10,x10,%pcrel_lo(.La1)
lw x11,0(x10)
addi x11,x11,1
sw x11,0(x10)
lw x10,-56(x8)
addi x10,x10,1
sw x10,-56(x8)
lw x10,-56(x8)
sw x10,-60(x8)
*addi x2,x8,0*
lw x11,-16(x2)
lw x10,-12(x2)
lw x8,-8(x2)
lw x1,-4(x2)
mret
Pascal Version:
procedure SysTick_interrupt; [interrupt, public, alias: 'MTIP_ISR'];
var
x : integer;
y : integer;
begin
Inc(SysTickCounter);
x := x+1;
y := x;
end;
Am 12.01.20 um 01:04 schrieb Michael Ring:
Here's my latest patch, I have included an (untested) unit for
gd32vf103 chips....
The defines for interrupts should be correct, but I did not start
testing if interrupts work. for the sifive chips the interrupts are
definitively wrong, but this will be my next step to fix as I work
more in the sifive board.
Have fun,
Michael
Am 04.01.20 um 13:50 schrieb Michael Ring:
The Boards are on their way, I found a second Sipeed MAIX board with
a Kendryte K210 chip, this should cover the 64bit World. Shipping
should take 3-5 days.
I will see that I can come up with a prelimary unit-file for the K210
Have fun with the boards,
Michael
Am 03.01.20 um 20:13 schrieb Jeppe Johansen:
Nice, thanks :)
Jeppe Johansen
Alexander Foss Gade 12, 3, 6
9000 Aalborg
Denmark
Hmm okay. Never seen a crash, but I haven't been using the 32bit
toolchain that much
Currently I use 2.32.51.20190629. Built from upstream
d6954c38df90637bc1b0cc2b20473e2754e5eff7
Best Regards,
Jeppe
On 1/3/20 7:41 PM, Michael Ring wrote:
I will be more than happy to provide a board to you.... Please send
me you smail address, will send you a board.
compiling now works fine with debuginfo but the linker crashes.
Most likely a problem in my linker script, just to be sure, which
binutils do you use?
Michael
Am 03.01.20 um 18:10 schrieb Jeppe Johansen:
Hi Michael,
I just fixed that. There was a very specific workaround in the fpc
dwarf writer but only riscv*-linux was added, not embedded.
I would be glad to buy a Longan Nano off you. Thought about
getting those before but never got around to ordering some.
Best Regards,
Jeppe
On 1/3/20 1:31 PM, Michael Ring wrote:
Things are slowly progressing for me, there is one thing that
bugs me, I cannot use Debug Info because I then get:
Error: non-constant .uleb128 is not supported
I found a few articles online on the issue and tried to replace
my default riscv32-embedded-as (built from latest gnu binutils)
with a version built out of the original risc-v git but this did
not change a thing.
Did you also encounter this? Which binutils package do you use?
If you are interested then I can send you a logan nano, I bought
three of them....
Happy new year,
Michael
Am 16.12.19 um 13:05 schrieb je...@j-software.dk:
Hi Michael
Looks like a good start. I have yet to get my hands on some
actual boards but I'll probably get some sipeeed ones soon
For the startup code the only tricky part is the initialization
of the GP register. The rest(init of .data and .bss) can be done
as Pascal code.
You can see how that's done in the Linux 64 startup code
We should probably add an intrinsic to read/write to the csrs in
case that's needed. Also for the other system instructions
Best regards,
Jeppe
-------- Original message --------
From: Michael Ring <m...@michael-ring.org>
Date: Sun, 15 Dec 2019, 20:57
To: je...@j-software.dk
Subject: Getting my feet wet with risc-v
Hi Jeppe,
hope all is fine with you!
I finally started to play arround with risc-v target, so far
I have added two boards (Units for boards are not final,
only a first try). I have a GD32VF103CBT6 based board
(Sipeed Longan Nano) and a sifive FE310-G002 based board
(HiFive1RevB) and now started with the HiFive Board as it
has a Segger JLink on-Board which will make debugging a lot
easier.
What I wanted to ask you, did you already create startup
code for riscv32/riscv64?
I am not yet very fluent in risc-v assembler so I wanted to
steal some code from you in case you have something.
Nevermind if you do not have something, it should be pretty
straightforward to port the arm startup code to risc-v
I still need to do the linker script in systems/t_embed.pp,
so do not expect too much from my patch ;-)
Michael
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